ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Bits
Description
[11]
STOP11
PDMA Channel 11 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 11 transfer. When user sets STOP11 bit,
the PDMA controller will stop the on-going transfer, then clear the channel enable bit
CHEN11 (PDMA_CHCTL [11]) and clear request active flag. If re-enable the stopped
channel again, the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 11 transfer.
[10]
STOP10
PDMA Channel 10 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 10 transfer. When user sets STOP10 bit,
the PDMA controller will stop the on-going transfer, then clear the channel enable bit
CHEN10 (PDMA_CHCTL [10]) and clear request active flag. If re-enable the stopped
channel again, the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 10 transfer.
[9]
STOP9
PDMA Channel 9 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 9 transfer. When user sets STOP9 bit, the
PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN9
(PDMA_CHCTL [9]) and clear request active flag. If re-enable the stopped channel again,
the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 9 transfer.
[8]
STOP8
PDMA Channel 8 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 8 transfer. When user sets STOP8 bit, the
PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN8
(PDMA_CHCTL [8]) and clear request active flag. If re-enable the stopped channel again,
the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 8 transfer.
[7]
STOP7
PDMA Channel 7 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 7 transfer. When user sets STOP7 bit, the
PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN7
(PDMA_CHCTL [7]) and clear request active flag. If re-enable the stopped channel again,
the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 7 transfer.
[6]
STOP6
PDMA Channel 6 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 6 transfer. When user sets STOP6 bit, the
PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN6
(PDMA_CHCTL [6]) and clear request active flag. If re-enable the stopped channel again,
the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 6 transfer.
[5]
STOP5
PDMA Channel 5 Transfer Stop Control Register (Write Only)
User can set this bit to stop the PDMA channel 5 transfer. When user sets STOP5 bit, the
PDMA controller will stop the on-going transfer, then clear the channel enable bit CHEN5
(PDMA_CHCTL [5]) and clear request active flag. If re-enable the stopped channel again,
the remaining transfers will be processed.
0 = No effect.
1 = Stop PDMA channel 5 transfer.
[4]
STOP4
PDMA Channel 4 Transfer Stop Control Register (Write Only)
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