ISD94100 Series Technical Reference Manual
Sep 9, 2019
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Rev1.09
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PDMA Address Stride Offset Control Register n (PDMA_ASOCRn)
Register
Offset
R/W Description
Reset Value
PDMA_ASOCR0
P 0x504 R/W Address Stride Offset Register of PDMA Channel 0
0x0000_0000
PDMA_ASOCR1
P 0x50C R/W Address Stride Offset Register of PDMA Channel 1
0x0000_0000
PDMA_ASOCR2
P 0x514 R/W Address Stride Offset Register of PDMA Channel 2
0x0000_0000
PDMA_ASOCR3
P 0x51C R/W Address Stride Offset Register of PDMA Channel 3
0x0000_0000
PDMA_ASOCR4
P 0x524 R/W Address Stride Offset Register of PDMA Channel 4
0x0000_0000
PDMA_ASOCR5
P 0x52C R/W Address Stride Offset Register of PDMA Channel 5
0x0000_0000
31
30
29
28
27
26
25
24
DASOL
11
22
21
20
19
18
17
16
DASOL
15
14
13
12
11
10
9
8
SASOL
7
6
5
4
3
2
1
0
SASOL
Bits
Description
[31:16]
DASOL
PDMA Destination Address Stride Offset Length
The 16-bit register defines the destination address stride transfer offset count of each row.
[15:0]
SASOL
PDMA Source Address Stride Offset Length
The 16-bit register defines the source address stride transfer offset count of each row.
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