ISD94100 Series Technical Reference Manual
Sep 9, 2019
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ADC Status Register 3 (EADC_STATUS3)
Register
Offset
R/W Description
Reset Value
EADC_STATUS3
0xFC
R
ADC Status Register 3
0x0000_001F
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved
CURSPL
Bits
Description
[31:5]
Reserved
Reserved. Any values read should be ignored. When writing to this field always write with
reset value.
[4:0]
CURSPL
ADC Current Sample Module
This register show the current ADC is controlled by which sample module control logic
modules.
If the ADC is Idle, this bit filed will set to 0x1F.
This is a read only register.
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