VeEX RXT-6000e, User Manual

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Frame 74 > ODI indicating to the far-end that AU/TU-AIS has been inserted into egressing AU-n
TU-n due to defects before or within the tandem connection
Frames 73-76 > Reserved capacity
V5 byte (LP signal label)
Byte contains error analysis, signal label and path status information
Continuous monitoring of anomalies or defects and payload composition at the path end or along the path
Bits 1-2 provides error checking (BIP-2)
Bit 3 is the LP-REI (0 = no error, 1 = errors)
Bit 4 is the LP-RFI (0 = no error, 1 = errors)
Bits 5-7 provide the VC-12 signal label
000 Unequipped
001 Equipped (non-specific)
010 Asynchronous
011 Bit synchronous
100 Byte synchronous
101 Extended
110 0.181 test signal (TSS4)
111 VC-AIS
Bit 8 is the VC12 path LP-RDI normally set to zero unless there is an error condition (AIS)
V5 Byte (VT signal label)
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J2 byte (LP)
Used to transmit a configurable 16-byte identifier that enables the receiving path to continuously verify its
connection with the transmitter
Uses the same byte structure as the J0 and J1 bytes
N2 byte (LP)
Provides LP/VT tandem connection monitoring function (LP-TCM) for the VC-11 and VC-12 levels
Bits 1-2: even parity error checking BIP-2 for the tandem connection
Bit 3: Set to “1”
Bit 4: Incoming AIS indicator (0 = no defect; 1 = defect occurred before tandem connection)
Bit 5: TC-REI indicating errored blocks caused in the tandem connection
Bit 6: OEI indicating errored blocks of the egressing VC-n
Bits 7-8: Operate in a 76 multi-frame structure:
Multiframe structure consists of:
RXT-6200_RXT6000e_Module_Manual Page 130 of 387