XC2200 Derivatives
System Units (Vol. 1 of 2)
Architectural Overview
User’s Manual
2-33
V2.1, 2008-08
ArchitectureX22, V1.1
2.5
Power Management
The XC2200 can operate within a wide supply voltage range from 3 V to 5 V. The internal
core supply voltage is generated via on-chip Embedded Voltage Regulators and is
supervised by on-chip Power Validation Circuits.
Two IO power domains help to reduce heat dissipation by supplying the major part of the
device with a low voltage (3 V), while still connecting analog 5 V sensor signals to the
ADCs (5 V).
The XC2200 provides several means to control the power it consumes either at a given
time or averaged over a certain timespan. Three mechanisms can be used (partly in
parallel):
•
Supply Voltage Management
allows the temporary reduction of the supply voltage
of major parts of the logic, or even the complete disconnection. This drastically
reduces the power consumed because of leakage current, in particular at high
temperature. The core logic is split into 2 core power domains, for this purpose.
Several power reduction modes provide the optimal balance of power reduction and
wake-up time.
•
Clock Generation Management
controls the distribution and the frequency of
internal and external clock signals. While the clock signals for currently inactive parts
of logic are disabled automatically, the user can reduce the XC2200’s CPU clock
frequency which drastically reduces the consumed power.
External circuitry can be controlled via the programmable frequency output EXTCLK.
•
Peripheral Management
permits temporary disabling of peripheral modules. Each
peripheral can separately be disabled/enabled.
Wake-up from power reduction modes can be triggered either externally by signals
generated by the external system, or internally by the on-chip wake-up timer, which
supports intermittent operation of the XC2200 by generating cyclic wake-up signals. This
offers full performance to quickly react on action requests while the intermittent sleep
phases greatly reduce the average power consumption of the system.
Note: When selecting the supply voltage and the clock source and generation method,
the required parameters must be carefully written to the respective bitfields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the intended operation of power supply system and clock system.
