XC2200 Derivatives
System Units (Vol. 1 of 2)
Central Processing Unit (CPU)
User’s Manual
4-1
V2.1, 2008-08
CPUSV2_X, V2.2
4
Central Processing Unit (CPU)
Basic tasks of the Central Processing Unit (CPU) are to fetch and decode instructions,
to supply operands for the Arithmetic and Logic unit (ALU) and the Multiply and
Accumulate unit (MAC), to perform operations on these operands in the ALU and MAC,
and to store the previously calculated results. As the CPU is the main engine of the
XC2200 microcontroller, it is also affected by certain actions of the peripheral
subsystem.
Because a five-stage processing pipeline (plus 2-stage fetch pipeline) is implemented in
the XC2200, up to five instructions can be processed in parallel. Most instructions of the
XC2200 are executed in one single clock cycle due to this parallelism.
This chapter describes how the pipeline works for sequential and branch instructions in
general, and the hardware provisions which have been made to speed up execution of
jump instructions in particular. General instruction timing is described, including standard
timing, as well as exceptions.
While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC) which is invoked automatically by the CPU whenever a code or data
address refers to the external address space.
Whenever possible, the CPU continues operating while an external memory access is in
progress. If external data are required but are not yet available, or if a new external
memory access is requested by the CPU before a previous access has been completed,
the CPU will be held by the EBC until the request can be satisfied. The EBC is described
in a separate chapter.
The on-chip peripheral units of the XC2200 work nearly independently of the CPU with
a separate clock generator. Data and control information are interchanged between the
CPU and these peripherals via Special Function Registers (SFRs).
Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt
Controller compares all pending peripheral service requests against each other and
prioritizes one of them. If the priority of the current CPU operation is lower than the
priority of the selected peripheral request, an interrupt will occur.
There are two basic types of interrupt processing:
•
Standard interrupt processing
forces the CPU to save the current program status
and return address on the stack before branching to the interrupt vector jump table.
•
PEC interrupt processing
steals only one machine cycle from the current CPU
activity to perform a single data transfer via the on-chip Peripheral Event Controller
(PEC).
System errors detected during program execution (hardware traps) and external non-
maskable interrupts are also processed as standard interrupts with a very high priority.
