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XC2200 Derivatives

System Units (Vol. 1 of 2)

The External Bus Controller EBC

 

User’s Manual

9-7

V2.1, 2008-08

EBC_X8, V1.0d1

 

9.2.2

Bus Cycle Phases

This chapter provides a detail description of each phase of an external memory bus
access cycle.

9.2.2.1

A Phase - CS Change Phase

The A phase can take 0-3 clocks. It is used for tristating databus drivers from the
previous cycle (tristate wait states after chip select switch).
A phase cycles are not inserted at every access cycle, but only when changing the CS.
If an access using one CS (CSx) ends and the next access with a different CS (CSy) is
started, then A phase cycles are performed according to the bits set in the 

first

 CS

(CSx). This feature is used to optimize wait states with devices having a long turn-off
delay at their databus drivers, such as EPROMs and flash memories.
The A phase cycles are inserted while the addresses and ALE of the next cycle are
already applied.
If there are some idle cycles between two accesses, these clocks are taken into account
and the A phase is shortened accordingly. For example, if there are three tristate cycles
programmed and two idle cycles occur, then the A phase takes only one clock.

9.2.2.2

B Phase - Address Setup/ALE Phase

The B phase can take 1-2 clocks. It is used for addressing devices before giving a
command, and defines the length of time that ALE is active. In multiplexed bus mode,
the address is applied for latching.

9.2.2.3

C Phase - Delay Phase

The C phase is similar to the A an B phases but ALE is already low. It can take 0-3 clocks.
In multiplexed bus mode, the address is held in order to be latched safely. Phase C
cycles can be used to delay the command signals (RW delay).

9.2.2.4

D Phase - Write Data Setup/MUX Tristate Phase

The D phase can take 0-1 clocks. It is used to tristate the address on the multiplexed bus
when a read cycle is performed. For all write cycles, it is used to ensure that the data are
valid on the bus before the command is applied.

9.2.2.5

E Phase - RD/WR Command Phase

The E phase is the command or access phase, and takes 1-32 clocks. Read data are
fetched, write data are put onto the bus, and the command signals are active. Read data
are registered with the terminating clock of this phase.
The READY function lengthens this phase, too. READY-controlled access cycles may
have an unlimited cycle time.

Summary of Contents for XC2200

Page 1: ...User s Manual V2 1 Aug 2008 Microcontrollers XC2200 Derivatives 16 32 Bit Single Chip Microcontroller with 32 Bit Performance Volume 1 of 2 System Units ...

Page 2: ...ry terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written ap...

Page 3: ...User s Manual V2 1 Aug 2008 Microcontrollers XC2200 Derivatives 16 32 Bit Single Chip Microcontroller with 32 Bit Performance Volume 1 of 2 System Units ...

Page 4: ...are Boot Support added 6 204 Description of register ISSR corrected 6 210ff Description of Double Watchdog Timer Error corrected 6 231ff Memory Content Protection added was in memory chapter before 8 2 Description of pin TRef updated 9 1ff Minor updates in description of EBC 10 2ff Status information added 10 29 Bootstrap loader information improved 11 1ff Minor updates in debug chapter We Listen ...

Page 5: ...1 Debug System 11 1 1 12 Instruction Set Summary 12 1 1 13 Device Specification 13 1 1 14 The General Purpose Timer Units 14 1 2 15 Real Time Clock 15 1 2 16 Analog to Digital Converter 16 1 2 17 Capture Compare Unit 2 17 1 2 18 Capture Compare Unit 6 CCU6 18 1 2 19 Universal Serial Interface Channel 19 1 2 20 Controller Area Network MultiCAN Controller 20 1 2 Keyword Index 21 1 2 Register Index 2...

Page 6: ...ces 2 9 1 2 2 On Chip System Resources 2 10 1 2 3 On Chip Peripheral Blocks 2 15 1 2 4 Clock Generation 2 32 1 2 5 Power Management 2 33 1 2 6 On Chip Debug Support OCDS 2 34 1 3 Memory Organization 3 1 1 3 1 Address Mapping 3 3 1 3 2 Special Function Register Areas 3 5 1 3 3 Data Memory Areas 3 9 1 3 4 Program Memory Areas 3 11 1 3 4 1 Program Data SRAM PSRAM 3 12 1 3 4 2 Non Volatile Program Mem...

Page 7: ... Program Flow Control 4 5 1 4 2 1 Branch Detection and Branch Prediction Rules 4 7 1 4 2 2 Correctly Predicted Instruction Flow 4 7 1 4 2 3 Incorrectly Predicted Instruction Flow 4 9 1 4 3 Instruction Processing Pipeline 4 11 1 4 3 1 Pipeline Conflicts Using General Purpose Registers 4 13 1 4 3 2 Pipeline Conflicts Using Indirect Addressing Modes 4 15 1 4 3 3 Pipeline Conflicts Due to Memory Bandw...

Page 8: ... 4 1 5 3 Interrupt Vector Table 5 11 1 5 4 Operation of the Peripheral Event Controller Channels 5 20 1 5 4 1 The PECC Registers 5 20 1 5 4 2 The PEC Source and Destination Pointers 5 24 1 5 4 3 PEC Transfer Control 5 26 1 5 4 4 Channel Link Mode for Data Chaining 5 28 1 5 4 5 PEC Interrupt Control 5 29 1 5 5 Prioritization of Interrupt and PEC Service Requests 5 31 1 5 6 Context Switching and Sav...

Page 9: ... Handling the Power System 6 109 1 6 5 5 Power State Controller PSC 6 111 1 6 5 6 Operating a Power Transfer 6 114 1 6 5 7 Power Control Registers 6 115 1 6 6 Global State Controller GSC 6 151 1 6 6 1 GSC Control Flow 6 151 1 6 6 2 GSC Registers 6 155 1 6 7 Software Boot Support 6 161 1 6 7 1 Start up Registers 6 161 1 6 8 External Request Unit ERU 6 162 1 6 8 1 Introduction 6 162 1 6 8 2 ERU Pin ...

Page 10: ...cation Block 6 246 1 6 15 3 Marker Memory 6 251 1 6 16 SCU Register Addresses 6 252 1 6 17 Implementation 6 260 1 6 17 1 Clock Generation Unit 6 260 1 6 17 2 ESR 6 261 1 7 Parallel Ports 7 1 1 7 1 General Description 7 2 1 7 1 1 Basic Port Operation 7 2 1 7 1 2 Input Stage Control 7 5 1 7 1 3 Output Driver Control 7 5 1 7 2 Port Register Description 7 6 1 7 2 1 Pad Driver Control 7 6 1 7 2 2 Port ...

Page 11: ...ion Registers ADDRSELx 9 23 1 9 3 7 Ready Controlled Bus Cycles 9 26 1 9 3 8 External Bus Arbitration 9 28 1 9 3 9 Shutdown Control 9 32 1 9 4 LXBus Access Control and Signal Generation 9 33 1 10 Startup Configuration and Bootstrap Loading 10 1 1 10 1 Start Up Mode Selection 10 1 1 10 2 Device Status after Start Up 10 2 1 10 2 1 Registers modified by the Start Up Procedure 10 2 1 10 2 2 System Fre...

Page 12: ... 4 GPT1 Auxiliary Timers T2 T4 Operating Modes 14 18 2 14 1 5 GPT1 Clock Signal Control 14 27 2 14 1 6 GPT1 Timer Registers 14 30 2 14 1 7 Interrupt Control for GPT1 Timers 14 31 2 14 2 Timer Block GPT2 14 32 2 14 2 1 GPT2 Core Timer T6 Control 14 34 2 14 2 2 GPT2 Core Timer T6 Operating Modes 14 38 2 14 2 3 GPT2 Auxiliary Timer T5 Control 14 41 2 14 2 4 GPT2 Auxiliary Timer T5 Operating Modes 14 ...

Page 13: ... 2 16 2 6 Request Source Arbiter 16 32 2 16 2 7 Arbiter Registers 16 36 2 16 2 8 Scan Request Source Handling 16 38 2 16 2 9 Scan Request Source Registers 16 42 2 16 2 10 Sequential Request Source Handling 16 46 2 16 2 11 Sequential Source Registers 16 51 2 16 2 12 Channel Related Functions 16 62 2 16 2 13 Channel Related Registers 16 67 2 16 2 14 Conversion Result Handling 16 77 2 16 2 15 Convers...

Page 14: ...Set Overview 18 2 2 18 1 2 Block Diagram 18 3 2 18 1 3 Register Overview 18 4 2 18 2 Operating Timer T12 18 7 2 18 2 1 T12 Overview 18 8 2 18 2 2 T12 Counting Scheme 18 10 2 18 2 3 T12 Compare Mode 18 14 2 18 2 4 Compare Mode Output Path 18 21 2 18 2 5 T12 Capture Modes 18 26 2 18 2 6 T12 Shadow Register Transfer 18 30 2 18 2 7 Timer T12 Operating Mode Selection 18 31 2 18 2 8 T12 related Register...

Page 15: ...sal Serial Interface Channel 19 1 2 19 1 Introduction 19 1 2 19 1 1 Feature Set Overview 19 2 2 19 1 2 Channel Structure 19 5 2 19 1 3 Input Stages 19 6 2 19 1 4 Output Signals 19 7 2 19 1 5 Baud Rate Generator 19 8 2 19 1 6 Channel Events and Interrupts 19 9 2 19 1 7 Data Shifting and Handling 19 9 2 19 2 Operating the USIC 19 13 2 19 2 1 Register Overview 19 13 2 19 2 2 Operating the USIC Commun...

Page 16: ...9 5 4 Data Flow Handling 19 173 2 19 5 5 IIC Protocol Registers 19 178 2 19 6 IIS Protocol 19 184 2 19 6 1 Introduction 19 184 2 19 6 2 Operating the IIS 19 188 2 19 6 3 Operating the IIS in Master Mode 19 193 2 19 6 4 Operating the IIS in Slave Mode 19 197 2 19 6 5 IIS Protocol Registers 19 198 2 19 7 USIC Implementation in XC2200 19 204 2 19 7 1 Implementation Overview 19 204 2 19 7 2 Channel Fe...

Page 17: ... 4 Message Object Registers 20 79 2 20 4 General Control and Status 20 102 2 20 4 1 Clock Control 20 102 2 20 4 2 Port Input Control 20 103 2 20 4 3 Suspend Mode 20 104 2 20 4 4 Interrupt Structure 20 105 2 20 5 MultiCAN Module Implementation 20 106 2 20 5 1 Interfaces of the CAN Module 20 106 2 20 5 2 Module Clock Generation 20 107 2 20 5 3 Mode Control Behavior 20 116 2 20 5 4 Mode Control 20 11...

Page 18: ...ormance goal Infineon has decided to develop its families of 16 32 bit CMOS microcontrollers without the constraints of backward compatibility wih previous architectures Nonetheless the architectures of these microcontroller families pursue successful hardware and software concepts which have been established in Infineon s popular 8 bit controller families while delivering 32 bit performance This ...

Page 19: ...ic Features on Page 1 5 lists the derivatives covered by this manual for a quick summary and comparison This manual is valid for these derivatives and describes all variations of the different available temperature ranges and packages For simplicity these various device types are referred to by the collective term XC2200 throughout this manual The complete Pro Electron conforming designations are ...

Page 20: ...tions become larger high level languages are favored by programmers because high level language programs are easier to write to debug and to maintain The C166 Family supports this starting with its 2nd generation The 80C166 type microcontrollers were the first generation of the 16 bit controller family These devices established the C166 architecture The C165 type and C167 type devices are members ...

Page 21: ...ed memories and peripherals allow compact systems the integrated core power supply and control reduces system requirements to one single voltage supply the powerful combination of CPU and MAC unit is unleashed by optimized compilers This leaves no performance gap towards 32 bit systems A variety of different versions is provided which offer various kinds of on chip program memory1 Mask programmabl...

Page 22: ...unit with different operating modes includes two 16 bit timers counters maximum resolution fSYS Up to Four Capture Compare Units for flexible PWM Signal Generation CCU6 3 6 Capture Compare Channels and 1 Compare Channel Two Multifunctional General Purpose Timer Units GPT1 three 16 bit timers counters maximum resolution fSYS 4 GPT2 two 16 bit timers counters maximum resolution fSYS 2 Six Serial Cha...

Page 23: ...ocessing Zero cycle jump execution Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flexible and efficient addressing modes for high code density Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags Hardware traps to identify exception conditions during runtime HLL support for semaphore operations an...

Page 24: ...interface to JTAG controller JTAG interface and break interface Hardware software and external pin breakpoints Up to 4 instruction pointer breakpoints Debug event control e g with monitor call or CPU halt or trigger of data transfer Dedicated DEBUG instructions with control via JTAG interface Access to any internal register or memory location via JTAG interface Single step support and watchpoints ...

Page 25: ...ality key tools such as compilers assemblers simulators debuggers or in circuit emulators Infineon incorporates its strategic tool partners very early into the product development process making sure embedded system developers get reliable well tuned tool solutions which help them unleash the power of Infineon microcontrollers in the most effective way and with the shortest possible learning curve...

Page 26: ...al Processing Unit DMU Data Management Unit EBC External Bus Controller ESFR Extended Special Function Register EVVR Embedded Validated Voltage Regulator Flash Non volatile memory that may be electrically erased GPR General Purpose Register GPT General Purpose Timer unit HLL High Level Language IIC Inter Integrated Circuit Bus IIS Inter Integrated Circuit Sound Bus IO Input Output JTAG Joint Test ...

Page 27: ...5 is referred to as P5 3 Where it helps to clarify the relation between several named structures the next higher level is added to the respective name to make it unambiguous The term ADC0_GLOBCTR clearly identifies register GLOBCTR as part of module ADC0 the term SYSCON0 CLKSEL clearly identifies bitfield CLKSEL as part of register SYSCON0 PLA Programmable Logic Array PLL Phase Locked Loop PMU Pro...

Page 28: ...the XC2200 is the LXBus an internal representation of the external bus interface This bus provides a standardized method for integrating additional application specific peripherals into derivatives of the standard XC2200 Figure 2 1 XC2200 Functional Block Diagram P3 P8 P11 Multi CAN C166SV2 Core DPRAM 2 Kbytes CPU PMU DMU BRGen ADC1 8 10 Bit 8 0 Chan USIC0 2 Ch 64 x Buffer RS232 LIN SPI IIC IIS RT...

Page 29: ...in superior CPU performance while maintaining C166 code compatibility Impressive DSP performance concurrent access to different kinds of memories and peripherals boost the overall system performance Figure 2 2 CPU Block Diagram DPRAM CPU IPIP RF R0 R1 GPRs R14 R15 R0 R1 GPRs R14 R15 IFU Injection Exception Handler ADU MAC mca04917_x vsd CPUCON1 CPUCON2 CSP IP Return Stack FIFO Branch Unit Prefetch...

Page 30: ... Unit Single cycle MAC instruction with zero cycle latency including a 16 16 multiplier 40 bit barrel shifter and 40 bit accumulator to handle overflows Automatic saturation to 32 bits or rounding included with the MAC instruction Fractional numbers supported directly One Finite Impulse Response Filter FIR tap per cycle with no circular buffer management Enhanced boolean bit manipulation facilitie...

Page 31: ... instructions are preprocessed in the branch detection unit to detect branches The prediction logic determines if branches are assumed to be taken or not FETCH The instruction pointer for the next instruction to be fetched is calculated according to the branch prediction rules The branch folding unit preprocesses detected branches and combines them with the preceding instructions to enable zero cy...

Page 32: ...o supported The Multiply and Accumulate Unit MAC performs extended arithmetic operations such as 32 bit addition 32 bit subtraction and single cycle 16 bit 16 bit multiplication The combined MAC operations multiplication with cumulative addition subtraction represent the major part of the DSP performance of the CPU The Address Data Unit ADU contains two independent arithmetic units to generate cal...

Page 33: ...nditional such as JMPI cc_UC Fixed prediction Branch instructions which are often used to realize loops are assumed to be taken if they branch backward to a previous location the begin of the loop This applies to conditional branches such as JMPR cc_XX or JNB Variable prediction In this case the respective prediction taken or not taken is coded into the instruction and can therefore be selected fo...

Page 34: ...odes which are not frequently used Consequently the instruction decode time decreases and the development of compilers and assemblers is simplified Provide most frequently used instructions with one word instruction formats All other instructions use two word formats This allows all instructions to be placed on word boundaries this alleviates the need for complex alignment hardware It also has the...

Page 35: ...fter being accepted by the CPU an interrupt service can be interrupted only by a higher prioritized service request For standard interrupt processing each of the interrupt nodes has a dedicated vector location Multiple Register Banks Two local register banks for immediate context switching add to a relocatable global register bank The user can specify several register banks located anywhere in the...

Page 36: ... on chip memory or from external memory The Data Management Unit DMU controls accesses to the on chip Data RAM DSRAM to the on chip peripherals connected to the peripheral bus and to resources on the external bus External accesses including accesses to peripherals connected to the on chip LXBus are executed by the External Bus Controller EBC The 16 bit interface between the DMU and the CPU handles...

Page 37: ...tor for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled in a manner similar to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter ...

Page 38: ...f on chip Dual Port RAM DPRAM are provided as a storage for user defined variables for the system stack and in particular for general purpose register banks A register bank can consist of up to 16 wordwide R0 to R15 and or bytewide RL0 RH0 RL7 RH7 so called General Purpose Registers GPRs The upper 256 bytes of the DPRAM are directly bitaddressable When used by a GPR any location in the DPRAM is bi...

Page 39: ...they should either not be accessed or written with zeros to ensure upward compatibility In order to meet the needs of designs where more memory is required than is provided on chip up to 12 Mbytes approximately see Table 2 1 of external RAM and or ROM can be connected to the microcontroller The External Bus Interface also provides access to external peripherals Table 2 1 XC2200 Memory Map Address ...

Page 40: ...000H 00 F1FFH 0 5 Kbyte XSFR area 00 E000H 00 EFFFH 4 Kbytes Data SRAM 00 A000H 00 DFFFH 16 Kbytes Reserved for DSRAM 00 8000H 00 9FFFH 8 Kbytes External memory area 00 0000H 00 7FFFH 32 Kbytes 1 The areas marked with are slightly smaller than indicated see column Notes 2 The uppermost 4 Kbyte sector of the first Flash segment is reserved for internal use C0 F000H to C0 FFFFH 3 Several pipeline op...

Page 41: ...exed demultiplexed the data bus width 8 bit 16 bit and even the length of a bus cycle waitstates signal delays can be selected independently This allows access to a variety of memory and peripheral components directly and with maximum efficiency Access to very slow memories or modules with varying access times is supported via a particular Ready function The active level of the control input signa...

Page 42: ...tive system The XC2200 generic peripherals are General Purpose Timer Unit GPT1 GPT2 Watchdog Timer Capture Compare Unit CAPCOM2 Up to Four Capture Compare Units CCU6 CCU60 CCU61 CCU62 CCU63 Two 10 bit Analog Digital Converters ADC0 ADC1 Real Time Clock RTC Thirteen Nine Parallel Ports with a total of 118 75 I O lines Because the LXBus is the internal representation of the external bus it does not ...

Page 43: ...ls can be disconnected from the clock signal either temporarily to save energy or permanently if they are not used in a specific application Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further details on peripheral timing are included in ...

Page 44: ...port generation and control of timing sequences on up to 16 channels with a maximum resolution of 1 system clock cycle 8 cycles in staggered mode The CAPCOM unit is typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PMW Digital to Analog D A conversion software timing or time recording relative to external events Two 16 bit timers T7 T8 with ...

Page 45: ...are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode Table 2 2 Compare Modes CAPCOM2 Compare Modes Function Mode 0 Interrupt only compare mode several compare interrupts per timer period are possible Mode 1 Pin toggles on each comp...

Page 46: ...ns CCx The output signals can be generated in edge aligned or center aligned PWM mode They are generated continuously or in single shot mode Compare timers T12 and T13 are free running timers which are clocked by the prescaled system clock For motor control applications brushless DC drives both subunits may generate versatile multichannel PWM signals which are basically either controlled by compar...

Page 47: ...gnal on a port pin TxEUD to facilitate e g position tracking In Incremental Interface Mode the GPT1 timers T2 T3 T4 can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD Direction and count signals are internally derived from these two input signals so the contents of the respective timer Tx corresponds to the sensor position The th...

Page 48: ...may be used to clock timer T5 and or it may be output on pin T6OUT The overflows underflows of timer T6 can additionally be used to clock the CAPCOM1 2 timers and to cause a reload from the CAPREL register The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin CAPIN and timer T5 may optionally be cleared after the capture proce...

Page 49: ... RTC timer block accessible via registers RTCH and RTCL made of a reloadable 10 bit timer a reloadable 6 bit timer a reloadable 6 bit timer a reloadable 10 bit timer All timers count up Each timer can generate an interrupt request All requests are combined to a common node request Note The registers associated with the RTC are not affected by an application reset in order to maintain the contents ...

Page 50: ... activated at the same time and then executed in a predefined sequence Queued requests are executed in a user defined sequence In addition the conversion of a specific channel can be inserted into a running sequence without disturbing this sequence All requests are arbitrated according to the priority level that has been assigned to them Data reduction features such as limit checking or result acc...

Page 51: ...r data frame 1 to 63 more with explicit stop condition MSB or LSB first IIC Inter IC Bus application baud rate 100 kBaud to 400 kBaud 7 bit and 10 bit addressing supported full master and slave device capability IIS infotainment audio bus module capability receiver with max baud rate fSYS module capability transmitter with max baud rate fSYS 2 application target baud rate range up to 26 MBaud In a...

Page 52: ...r frames even unlimited length or frames with a dynamically controlled length Interrupt capability The events of each USIC channel can be individually routed to one of 4 service request outputs depending on the application needs Furthermore specific start and end of frame indications are supported in addition to protocol specific events Flexible interface routing Each USIC channel offers the choic...

Page 53: ... maximum reachable baud rate due to driver delays signal propagation times or due to EMI reasons Note Depending on the selected additional functions such as digital filters input synchronization stages sample point adjustment data structure etc the maximum reachable baud rate can be limited Please also take care about additional delays such as internal or external propagation delays and driver del...

Page 54: ...pecific actions are handled by protocol pre processors PPP In order to simplify data handling an additional FIFO data buffer is optionally available for each USIC module to store transmit and receive data for each channel This FIFO data buffer is not necessarily available in all devices please refer to USIC implementation chapter for details Due to the independent channel control and baud rate gen...

Page 55: ...age object can be individually allocated to one of the CAN nodes Besides serving as a storage container for incoming and outgoing frames message objects can be combined to build gateways between the CAN nodes or to setup a FIFO buffer The message objects are organized in double chained linked lists where each CAN node has its own list of message objects A CAN node stores frames only into message o...

Page 56: ... monitoring Watchdog Timer The Watchdog Timer represents one of the fail safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time The Watchdog Timer is always enabled after a reset of the chip and can be disabled and enabled at any time by executing instructions DISWDT and ENWDT Thus the chip s start up procedure is always monitored The s...

Page 57: ... the internal reset all port pins are configured as inputs without pull devices active All port lines have programmable alternate input or output functions associated with them These alternate fucntions can be assigned to various port pins to support the optimal utilization for a given application For this reason certain functions appear several times in Table 2 3 All port lines that are not used ...

Page 58: ...put Output lines for CCU62 Timer control signals JTAG OCDS control system clock output Port 8 7 Input Output lines for CCU60 JTAG OCDS control Port 9 8 Serial interface lines of USIC2 Input Output lines for CCU60 and CCU63 OCDS control Port 10 16 16 Address and or data lines bus control Serial interface lines of USIC0 USIC1 CAN2 CAN3 and CAN4 Input Output lines for CCU60 JTAG OCDS control Port 11 ...

Page 59: ...ernal system The system clock fSYS can be derived from several internal and external clock sources The on chip high precision oscillator OSC_HP can drive an external crystal or accepts an external clock signal The oscillator clock frequency can be multiplied by the on chip PLL by a programmable factor or can be divided by a programmable prescaler factor An internal clock source can provide a clock...

Page 60: ...ptimal balance of power reduction and wake up time Clock Generation Management controls the distribution and the frequency of internal and external clock signals While the clock signals for currently inactive parts of logic are disabled automatically the user can reduce the XC2200 s CPU clock frequency which drastically reduces the consumed power External circuitry can be controlled via the progra...

Page 61: ...ally the OCDS system can be controlled by the CPU e g by a monitor program An injection interface allows the execution of OCDS generated instructions by the CPU Multiple breakpoints can be triggered by on chip hardware by software or by an external trigger input Single stepping is supported as well as the injection of arbitrary instructions and read write access to the complete internal address sp...

Page 62: ...pecial Function Register Areas SFRs and ESFRs the internal IO area and external memory are mapped into one common address space Figure 3 1 Address Space Overview External Memory Area On Chip Program Memory Areas mc_xc16x_mmap vsd 239 224 223 208 191 176 175 160 159 144 143 128 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 00 0000H C0 0000H FF FFFF H 40 0000 H 80 0000 H 16 Mbytes Total Addressi...

Page 63: ...sition at a word address Bit position 0 is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit addressing is supported for a part of the Special Function Registers a part of the internal RAM and for the General Purpose Registers Figure 3 2 Storage of Words Bytes and Bits in a Byte Organized Memor...

Page 64: ...EPSRAM Emulated PSRAM E8 0000H E8 FFFFH 64 KBytes With Flash timing Reserved for PSRAM E1 0000H E7 FFFFH 448 KBytes Mirrors PSRAM PSRAM E0 0000H E0 FFFFH 64 KBytes Program SRAM Reserved for Flash CC 0000H DF FFFFH 1 25 MBytes Flash 2 C8 0000H CB FFFFH 256 KBytes Flash 1 C4 0000H C7 FFFFH 256 KBytes Flash 0 C0 0000H C3 FFFFH 252 KBytes3 Minus res seg External memory area 40 0000H BF FFFFH 8 MBytes ...

Page 65: ...bus interface these accesses generate external bus accesses 2 The areas marked with are slightly smaller than indicated see column Notes 3 The uppermost 4 Kbyte sector of the first Flash segment is reserved for internal use C0 F000H to C0 FFFFH 4 Several pipeline optimizations are not active within the external IO area This is necessary to control external peripherals properly ...

Page 66: ...rea located in FF FF00H FF FFFFH 1 This arrangement provides upward compatibility with the derivatives of the C166 and XC166 families Figure 3 3 Special Function Register Mapping Note The upper 256 bytes of SFR area ESFR area and internal RAM are bit addressable see hashed blocks in Figure 3 3 1 Attention the IMB SFR area is not recognized by the CPU as special IO area see Section 3 6 xc2000_regar...

Page 67: ...g mechanism from the standard SFR area to the Extended SFR area This is not required for 16 bit and indirect addresses The GPRs R15 R0 are duplicated i e they are accessible within both register blocks via short 2 4 or 8 bit addresses without switching ESFR_SWITCH_EXAMPLE EXTR 4 Switch to ESFR area for next 4 instr MOV STMREL data16 STMREL uses 8 bit reg addressing BFLDL STMCON mask data8 Bit addr...

Page 68: ...trast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 bytes The GPRs are accessed via short 2 4 or 8 bit addressing modes using the Context Pointer CP register as base address for the global bank independent of the current DPP register contents Additionally each bit in the currently active register bank can be accessed indivi...

Page 69: ...urce and destination address pointers for data transfers on the PEC channels are located in the XSFR area Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer SRCPx on the lower and the destination pointer DSTPx on the higher word address x 7 0 An additional segment register stores the associated source and destination segments so PEC transfers can m...

Page 70: ...ts to data page 3 Any word data access is made on an even byte address The highest possible word data storage location in the DPRAM is 00 FDFEH For PEC data transfers the DPRAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The upper 256 bytes of the DPRAM 00 FD00H through 00 FDFFH are provided for single bit storage and thus they are b...

Page 71: ...wer domain DMP_1 is switched off Unlike the other memories the SBRAM is not mapped into the address range of the processor Reading and writing is done via two address and two data SFRs Details of the access mechanism are described in Section 3 11 Note Code cannot be executed out of the SBRAM Marker Memory MKMEM The MKMEM provides 4 bytes of memory supplied by the wake up power domain Its purpose i...

Page 72: ...and other data For example higher level boot loader software can be written to the PSRAM and then be executed to program the on chip Flash memory Figure 3 4 On Chip Program Memory Mapping Reserved Reserved PSRAM Reserved PSRAM Reserved Flash Area Reserved Flash 0 252 KB Flash 1 256 KB Flash 2 256 KB C0 0000H D0 0000H E0 0000H F0 0000H FF FF00 H PSRAM 64 KB SRAM Timing E0 0000H E1 0000H E8 0000H im...

Page 73: ...location E0 0000H An area of 512 Kbytes is dedicated to PSRAM E0 0000H F7 FFFFH The locations without implemented PSRAM are reserved Flash Emulation During code development the PSRAM will often be used for storing code or data that the production chip will later contain in the flash memory In order to ensure similar execution time the PSRAM supports a second access path in the range E8 0000H EF FF...

Page 74: ...split the PSRAM into a read only and a writable part Write accesses to the read only part are blocked and a trap can be activated 3 4 2 Non Volatile Program Memory Flash The XC2200 provides up to 764 Kbytes of program Flash C0 0000H CB FFFFH Code and data fetches are always 64 bit aligned using byte select lines for word and byte data Any word or byte data in the program memory can be accessed via...

Page 75: ...tack Register SP is decremented before data is pushed on the system stack and incremented after data has been pulled from the system stack Only word accesses are supported to the system stack By using register SP for stack operations the size of the system stack is limited to 64 KBytes The stack must be located in the segment defined by register SPSEG The stack pointer points to the latest system ...

Page 76: ...FH 512 bytes The XSFR area located from 00 E000H to 00 EFFFH 4 Kbytes Note The external IO area supports real byte accesses The internal IO area does not support real byte transfers the complementary byte is cleared when writing to a byte location The IO areas have special properties because peripheral modules must be controlled in a different way than memories Accesses are not buffered and cached...

Page 77: ...6 on Port 4 and A15 A0 on PORT0 or PORT1 8 bit segmented mode 12 Mbytes with A23 A16 on Port 4 and A15 A0 on PORT0 or PORT1 Each bank can be directly addressed via the address bus while the programmable chip select signals can be used to select various memory banks The XC2200 also supports four different bus types Multiplexed 16 bit Bus with address and data on PORT0 default after Reset Multiplexe...

Page 78: ...ry area to the on chip RAM area takes place within segment 0 Segments are contiguous blocks of 64 Kbytes each They are referenced via the Code Segment Pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and R...

Page 79: ...nt can not be changed directly as in SRAMs Changing data is a complicated process with a typically much longer duration than reading Erasing The erased state of a cell is logical 0 Forcing an flash cell to this state is called erasing Erasing is possible with a minimum granularity of one page see below A device is delivered with completely erased flash memory Programming The programmed state of a ...

Page 80: ...in the data sheet Attention No means exist in the device that prevent the application from violating these limitation Array Structure The flash memory is hierarchically structured Block A block consists of 128 user data bits i e 16 bytes and 9 ECC bits One read access delivers one block Page A page consists of 8 blocks i e 128 bytes Programming changes always complete pages Sector A sector consist...

Page 81: ...will be discussed here 3 9 2 1 Standard Read Mode After reset and after performing a clean startup the flash memory with all its modules is in standard read mode In this mode it behaves as an on chip ROM This mode is entered After reset when the complete start up has been performed After completion of a longer lasting command like erase or program which is acknowledged by clearing the busy flag Im...

Page 82: ...t accepted even if they target different flash modules and cause a sequence error until the running operation has finished Read accesses to busy flash modules stall the CPU until the read mode is entered again A stalled CPU responds only to the reset As no interrupts can be handled this state must be avoided Nevertheless this feature can be used to execute code from a flash module that erases or p...

Page 83: ...to the PMU The complete 128 data bits and the 9 ECC bits are stored in the IMB Core with their address If a succeeding fetch request matches this address the data is delivered from the buffer without performing a read access in the flash memory The delivery from the buffer happens after one cycle The flash read wait cycles are not waited The stored data are a kind of instruction cache In order to ...

Page 84: ...livered after one cycle from the data register Every data read that is not delivered from this cache invalidates the cache content When the requested data arrives the cache contains again valid data This small data cache is invalidated when a write i e erase or program access to this address happens For data reads the IMB Core does not perform any autonomous pre fetching 3 9 3 3 Data Writes to Fla...

Page 85: ...n Change read margins Page 3 26 Enter Page Mode Prepare page for programming Page 3 27 Enter Security Page Mode Prepare security page for programming Page 3 28 Load Page Word Load page with data Page 3 28 Program Page Start page programming process Page 3 29 Erase Sector Start sector erase process Page 3 30 Erase Page Start page erase process Page 3 31 Erase Security Page Start security page erase...

Page 86: ...ta word that is written into the assembly buffer SA Sector Address This is the physical sector number as defined in Figure 3 6 based on the address of the flash module Two examples as clarification 1 Physical sector number 16 of the first array that is based on C0 0000H is addressed with SA C0 0000H 16 4 1024 C1 0000H 2 The second 256 KB array has the base address C4 0000H as shown in Table 3 1 So...

Page 87: ...state It clears also all error flags in the Flash Status Register IMB_FSR and an active page mode is aborted Because all commands are rejected with a SQER while the IMB Core is busy Reset to Read can not be used to abort an active command mode This command clears PROER PAGE SQER OPER ISBER IDBER DSBER DDBER Clear Status Arguments Definition MOV XXAAH XXF5H Timing 1 cycle command that does not set ...

Page 88: ... of its block assembly register to zero so that it points to the first word The page mode is indicated in the status register IMB_FSR with the PAGE bit separately for each flash module The page mode and the read mode are allowed in parallel at the same time and in the same flash module so the flash module stays readable When the addressed page PA is read the content of the flash memory is delivere...

Page 89: ...rd Arguments WD Definition MOV XXF2H WD Timing 1 cycle command that does not set any BUSY flags But note that an immediately following write access to the IMB Core or read from the flash memory is stalled for a few clock cycles if it arrives while the IMB Core is busy with copying its block assembly register content into the flash module assembly buffer During this stall time the CPU can not perfo...

Page 90: ...s are used the additional data is lost The overflow condition is indicated by the sequence error flag but the execution of a following Program Page command is not suppressed the page mode is not aborted When a Load Page Word command is received and the flash is not in page mode a sequence error is reported in IMB_FSR with SQER flag In case of a new Enter Page Mode command or a Reset to Read comman...

Page 91: ...ode see description of the Enter Page Mode command If the page to be programmed is a security page accepted only in security page mode the new protection configuration including keywords or protection confirmation code is valid directly after execution of this command While the IMB Core reads the new protection configuration all DMU accesses to any flash module are stalled Erase Sector Arguments S...

Page 92: ...inition MOV XXAAH XX80H MOV XX54H XXAAH MOV PA XX03H Timing 3 cycle command that sets BUSY for the whole erasing duration Description The addressed page is erased Following data reads deliver all zero data with correct ECC With the last cycle of the Erase Page command the command mode is entered indicated by activation of the ERASE flag and after start of erase operation also by the related BUSY f...

Page 93: ...n Page 3 43 After erasing a security page the new protection configuration including keywords or protection confirmation code is valid directly after execution of this command While the IMB Core reads the protection configuration all DMU accesses to any flash module are stalled This command must not be issued when the flash memory is in page mode In this case it is ignored and a sequence error is ...

Page 94: ...nd the read protection disable bit RPRODIS is set in the Flash Status Register IMB_FSR Erase and program operations on all sectors are then possible if the flash memory was also globally write protected WPA 1 and if they are not separately write protected The read protection including global write protection if so selected remains disabled until the command Re Enable Read Write Protection is execu...

Page 95: ...hat does not set any busy flags Description Flash read and write protection is resumed This single cycle command clears RPRODIS and WPRODIS The IMB Core is triggered to restore the protection states RPA and WPA from the content of the security page 0 as defined in Table 3 4 Flash State Determining RPA and WPA on Page 3 40 So in effect this command resumes all kinds of temporarily disabled protecti...

Page 96: ...gram Erase Detection Where the ECC should protect from intrinsic failures of the flash memory that affect usually only single bits an interruption of a running program or erase process might cause massive data corruption The erase process programs first all cells to 1 before it erases them So depending on the time when it is interrupted the data might be in a different state This can be the old da...

Page 97: ...such cases can be increased Reading with hard read 0 margin returns weak 0s as 1s and reading with hard read 1 margin returns weak 1s as 0s Changing the read margin is done with the command sequence Change Read Margin and is reported by the status register IMB_MAR 3 9 5 4 Protection Overview The flash memory supports read and write protection for the whole memory and separate write protection for ...

Page 98: ...ed programming or erase accesses and to provide virus proof protection for all sectors Read and write protection is installed by specific security configuration words which are programmed by the user directly into two Security Pages SecP0 1 After any reset the security configuration is checked by the command state machine IMB Core and installations are stored and indicated in related registers If ...

Page 99: ...ate IMB_FSR The protection state can be temporarily changed with command sequences which is reflected in the IMB_FSR The highest layer is represented by 4 fields of the IMB_IMBCTR register These fields define the protection rights of the customer software are read or write accesses currently allowed or not The IMB Core controls the protection state of all connected flash modules centrally In this ...

Page 100: ...tected state protection installed state or errored protection state These states are reflected in the register settings of the next layer The device is usually delivered in the non protected state The exact layout of the security pages is described in Layout of the Security Pages on Page 3 43 3 9 6 2 The Middle Layer Flash State The middle layer consists of the registers IMB_PROCONx and IMB_FSRx a...

Page 101: ...s WPRODIS to 1 if the correct passwords are supplied It behaves analog to RPRODIS as described above The command Re Enable Read Write Protection clears RPRODIS and WPRODIS The commands Enter Page Mode Enter Security Page Mode Erase Page Erase Security Page and Erase Sector set PROER if the write access to the addressed range is not allowed If a write access is allowed or not is determined by the n...

Page 102: ...e recognized as attacked state Effective Security Level The effective security level based on these 4 double bits is summarized in Table 3 5 and Table 3 6 For the double bits the same short notation is used as before 1 means active 0 means inactive means invalid and means do not care including invalid states 0 1 Errored protection state see below 0 0 RPA 1 WPA 1 0 1 RPA 1 WPA 0 1 0 RPA 0 WPA 1 1 1...

Page 103: ...RPA and WPA according to the rules of Table 3 4 The bits DDF and DCF of the IMB_IMBCTR are not initialized by the IMB Core During system startup they are initialized depending on the startup condition If code fetching starts in the flash memory then they are set to the inactive state In all other cases they are activated to prevent read access to the flash memory without proving password knowledge...

Page 104: ...ples in Protection Handling Examples on Page 3 45 will show how this can be used for installing and removing protection or changing passwords 3 9 6 4 Reaction on Protection Violation If software tries to violate the protection rules the following happens Reading data when read protection is effective The bit IMB_FSR PROER is set and the Flash access trap can be triggered via the SCU if IMB_INTCTR ...

Page 105: ... CH Both contain AA55H to form the correct lock code All bytes of the used blocks of the security pages block 0 and 1 of SecP0 and block 0 of SecP1 are to be considered as reserved and must be kept erased i e with all zero content The unused blocks of the security pages blocks 2 to 7 of SecP0 and blocks 1 to 7 of SecP1 shall be programmed with all one data Block 1 7 unused Block 2 7 unused CH RPRO...

Page 106: ...alid state After finishing the erase command the IMB Core restores the IMB_FSR and IMB_IMBCTR fields from the flash data Because no lock code is present in SecP1 the invalid state of RPRO has no effect on the user visible protection Still all parts of the flash memory can be written The second step is to program the information of SecP0 with the required security information Again the IMB Core rea...

Page 107: ...d state the SecP1 contains the lock code First write protection must be disabled with the correct passwords Then the lock code in SecP1 is erased If this operation was successful PROIN will be cleared by the IMB Core Now SecP0 can be safely erased From this point on the security pages are in the factory delivery state and the new passwords and security settings can be installed as described above ...

Page 108: ...ially interrupt requests must still be serviced This requirement is fulfilled in the XC2200 because all three flash modules work independently If one is busy with program or erase then code can still be executed from the other two The other requirements are more difficult to fulfill because the XC2200 does not have an EEPROM available but only the flash memory with the already frequently mentioned...

Page 109: ...ata is unstable e g changing operating conditions cause read errors If the power is cut early the page can appear as erased although some cells are partly programmed When programming different data to this apparently erased page read errors might occur Power is cut during erase the same as above can happen Data may appear as erased but the retention is lowered A power failure during a page erase c...

Page 110: ...comes 1 and IEN was already 1 No interrupt is sent when IEN becomes 1 when ISR was already 1 or both are set to 1 at the same time 3 9 10 Recommendations for Optimized Flash Usage This section describes best practices for using the flash in certain application scenarios e g how to use effectively ECC and margin reads For a description of the hardware features consult Data Integrity on Page 3 35 3 ...

Page 111: ...eshold of allowed single bit errors could be increased for in service updates in order to reduce the risk of false negatives 3 9 10 2 EEPROM Emulation For EEPROM emulation the goal is usually not readability over device life time but highest possible robustness against violated operating conditions power failures even failing flash pages e g due to over cycling The risk of false negatives should b...

Page 112: ...ion code data or a mixture of both The IMB manages accesses to the memories and supports flash programming and erase 3 10 1 Overview The Figure 3 9 shows how the IMB and its memories are integrated into the device architecture Only the main data streams are included The data buses are usually accompanied by address and control signals and check sum data like parity or ECC Figure 3 9 IMB Block Diag...

Page 113: ...its Write accesses address as well 16 bit words but additional byte enables allow changing single bytes Because of the CPU s von Neumann architecture data and instructions and special function registers to complete the list share a common address range When instructions are used as data e g when copying code from an IO interface to the PSRAM they are accessed via the data bus The pipelined behavio...

Page 114: ...lease note that the register write protection is not activated automatically again after an access to IMB_IMBCTR because this happens only for SCU internal registers Table 3 7 Registers Overview Register Short Name Register Long Name Offset Address Page Number IMB_IMBCTRL IMB Control Low FF FF00H Page 3 53 IMB_IMBCTRH IMB Control High FF FF02H Page 3 55 IMB_INTCTR Interrupt Control FF FF04H Page 3...

Page 115: ... is disabled Usually for code with power minimization requirements or for code with short linear code sections this feature should be disabled DLCPF 1 Enabling this feature is only advantageous for code section with longer linear sequences With lower values of WSFLASH the performance gain of DLCPF 0 is reduced In case of low WSFLASH settings DLCPF 1 might even lead to better performance than with ...

Page 116: ...ion Reset During startup or test mode or when RPA 0 software can change this field to any value Otherwise data reads can only be disabled but not enabled anymore until the next Application Reset IMB_IMBCTRH IMB Control High ISFR FF FF02H Reset value 0005H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSPROT RPA WPA rw rh rh Field Bits Typ Description WPA 1 0 rh Write Protection Activated 01 Short notation...

Page 117: ...M Write Protection This 8 bit field determines the address up to which the PSRAM is write protected The start address of the writable range is E0 0000H 1000H PSPROT The end address is determined by the implemented memory The equivalent range in the PSRAM area with flash access timing is protected as well Here the writable range starts at E8 0000H 1000H PSPROT and ends at E8 FFFFH for XC2200 So wit...

Page 118: ...n with 1 the ISR is cleared Reading this bit delivers always 0 Writing a 0 is ignored ISET 9 w Interrupt Set When written with 1 the ISR is set and if IEN is set the interrupt signal is activated Reading this bit delivers always 0 Writing a 0 is ignored When writing ISET and ICLR to 1 concurrently ISET takes priority so ISR is set PSERCLR 10 w Clear PSRAM Error Flag When written with 1 the PSER is...

Page 119: ... 0 rh Busy A flash module is busy with a task Each bit position corresponds to one of the 3 flash modules The task is indicated by the bits MAR POWER ERASE or PROG of IMB_FSR_OP BUSY is automatically cleared when the task has finished The corresponding task indication is not cleared in order to allow an interrupt handler to determine the finished task PAGE 10 8 rh Page Mode Indication Set as long ...

Page 120: ... must be cleared by a Clear Status command This bit is not cleared by an Application Reset but only by a System Reset POWER 2 rh Power Change Indication This bit indicates that a flash module is in its startup phase or in a shutdown phase The BUSY bits indicate which flash module is busy This bit is not automatically reset but must be cleared by a Clear Status command MAR 3 rh Margin Change Indica...

Page 121: ...ash State Protection ISFR FF FF0AH Reset value x000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RPRO DDB ER DSB ER IDBE R ISBE R PRO ER WPR ODIS RPR ODIS PROI NER PROI N rh rh rh rh rh rh rh rh rh rh Field Bits Typ Description PROIN 0 rh Flash Protection Installed Modified by the IMB Core Cleared by Application Reset PROINER 1 rh Flash Protection Installation Error Modified by the IMB Core Cleared by A...

Page 122: ... Error Set by a violation of the installed protection Reset by the Clear Status and Reset to Read commands or an Application Reset ISBER 8 rh Instruction Fetch Single Bit Error Set if during instruction fetch a single bit ECC error was detected and corrected Reset by Clear Status or Reset to Read commands or an Application Reset IDBER 9 rh Instruction Fetch Double Bit Error Set if during instructi...

Page 123: ...s to the corresponding logical sector this means to the range of physical sectors is locked under the conditions that are documented in Protection Handling Details on Page 3 38 The PROCON registers are exclusively modified by the IMB Core Reset by Application Reset IMB_MAR Margin Control ISFR FF FF0CH Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HREAD2 HREAD1 HREAD0 rh rh rh Field Bits ...

Page 124: ... 3 IMB_PROCONx x 0 2 Protection Configuration ISFR FF FF10H 2 x Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S9U S8U S7U S6U S5U S4U S3U S2U S1U S0U rh rh rh rh rh rh rh rh rh rh Field Bits Typ Description SsU s 0 9 s rh Sector 0 to 9 Unlock s Logical sector s of flash module 0 is write protected ...

Page 125: ...disabled in the Clock off Mode The second useful value is 10B This value must be used in all cases when the Clock off Mode is accompanied by disabling the system clock of the DMP_1 This register gets is reset by an Application Reset Attention the reset value of COMCFG is 00B The access to this register is controlled by the register security mechanism Sec type Table 3 8 Registers Address Space Modu...

Page 126: ...he shutdown request is activated in clock off mode If COMCFG 13 is 1 the shutdown request is activated in clock off mode i e CR 10 COMCFG 12 has no functionality BPCOM 15 w Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG It always reads 0 It is only active during the write access cycle 0 The bit field COMCFG is not changed 1 The bit field COMCFG is updated with ...

Page 127: ...tection for NOMCFG This bit enables the write access to the bit field NOMCFG It always reads 0 It is only active during the write access cycle 0 The bit field NOMCFG is not changed 1 The bit field NOMCFG is updated with the written value SUMCFG 9 8 rw Suspend Mode Configuration This bit field defines if the power down request is activated in suspend mode which makes only sense if it is activated i...

Page 128: ...d in clock off mode If COMCFG 13 is 1 the power down request is activated in clock off mode i e CR 10 COMCFG 12 has no functionality BPCOM 15 w Bit Protection for COMCFG This bit enables the write access to the bit field COMCFG It always reads 0 It is only active during the write access cycle 0 The bit field COMCFG is not changed 1 The bit field COMCFG is updated with the written value Field Bits ...

Page 129: ...rganization User s Manual 3 68 V2 1 2008 08 MemoryX2K V1 3 3 10 3 Startup Shutdown The startup and shutdown of memories and the processor sub system is described in the Programmier s Guide Also the use of the Kernel Control registers is described there ...

Page 130: ...emory with single bit error Silently corrected Bit IMB_FSR ISBER set Instruction fetch from flash memory with double bit error Bit IMB_FSR IDBER set If IMB_INTCTR DIDTRP 0 TRAP 15D delivered instead of corrupted data Data read from protected flash memory IMB_FSR PROER set If IMB_INTCTR DPROTRP 0 Flash access trap1 and default data is delivered Instruction fetch from protected flash memory TRAP 15D...

Page 131: ...down flash modules Considered as access to not implemented memory range Default data or data from implemented flash modules will be returned Instruction fetch from powered down flash modules Considered as access to not implemented memory range Default data TRAP 15D will be returned or data from implemented flash modules Program or erase command targeting powered down flash modules Silently ignored...

Page 132: ...atically incremented by 1 one word for the next data to be stored The address pointer automatically does a wrap around after reaching its maximum value and in this case bit WADD WA is set Bit WADD MOD is set by a write access to DATA1 Read without automatic increment of the read address pointer The SW has to write the target address first to RADD and then can read the data from DATA0 If DATA0 is r...

Page 133: ...K V1 3 from write to read accesses SBRAM_RADD should be written again before reading SBRAM_DATAx Note Because of this pre reading feature and the auto increment behavior it is important to initialize always the address following the last data in order to prevent parity ECC errors due to this pre reading ...

Page 134: ...FEDEH Page 3 74 SBRAM_DATA0 SBRAM Data Register 0 FEE0H Page 3 76 SBRAM_DATA1 SBRAM Data Register 1 FEE2H Page 3 77 SBRAM_RADD SBRAM Read Address RegisterSFR FEDCH 6EH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD WA 0 RPTR 0 rwh rwh r rwh r Field Bits Type Description RPTR 9 1 rwh Read Pointer Selects the word address to be read from the SBRAM It is automatically incremented by 1 i ...

Page 135: ...1 and RPTR was automatically incremented by 1 0 0 13 10 r Reserved Read as 0 should be written with 0 SBRAM_WADD SBRAM Write Address RegisterSFR FEDEH 6FH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOD WA 0 WPTR 0 rwh rwh r rwh r Field Bits Type Description WPTR 9 1 rwh Write Pointer Selects the write word address within the SBRAM It is automatically incremented by 1 if register DATA1...

Page 136: ...ates whether the last write access to SBRAM data lead to an automatic increment of WPTR 0 The last data write access was done to DATA0 and WPTR was not modified automatically 1 The last data write access was done to DATA1 and WPTR was automatically incremented by 1 0 0 13 10 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 137: ...egister 0 SFR FEE0H 70H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA rwh Field Bits Type Description DATA 15 0 rwh SBRAM Data This bit field contains the data read during the latest SBRAM read access and is the target for the data to be written to SBRAM A read access always delivers the data stored in the SBRAM at the address indicated by the read pointer RADD RPTR A write access o...

Page 138: ...r 1 SFR FEE2H 71H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA rwh Field Bits Type Description DATA 15 0 rwh SBRAM Data This bit field contains the data read during the latest SBRAM read access and is the target for the data to be written to SBRAM A write access of at least the low byte leads to the storage of the written data at the address indicated by the write pointer WADD WPTR...

Page 139: ...ver a code or data address refers to the external address space Whenever possible the CPU continues operating while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous access has been completed the CPU will be held by the EBC until the request can be satisfied The EBC is descri...

Page 140: ...ol PSW CPUCON1 CPUCON2 Code Access Control IP CSP Data Paging Control DPP0 DPP1 DPP2 DPP3 Global GPRs Access Control CP System Stack Access Control SP SPSEG STKUN STKOV Multiply and Divide Support MDL MDH MDC Indirect Addressing Offset QR0 QR1 QX0 QX1 MAC Address Pointers IDX0 IDX1 MAC Status Indication and Control MCW MSW MAH MAL MRW ALU Constants Support ZEROS ONES The CPU also uses CSFRs to acc...

Page 141: ...s a non critical operation Any write operation to a single byte of a CSFR clears the non addressed complementary byte within the specified CSFR Attention Reserved CSFR bits must not be modified explicitly and will always supply a read value of 0 If a byte word access is preferred by the programmer or is the only possible access the reserved CSFR bits must be written with 0 to provide compatibility...

Page 142: ...ultiply and Accumulate Unit handle differently sized data and execute complex operations Three memory interfaces and Write Buffer minimize CPU stalls due to data transfers Figure 4 1 CPU Block Diagram DPRAM CPU IPIP RF R0 R1 GPRs R14 R15 R0 R1 GPRs R14 R15 IFU Injection Exception Handler ADU MAC mca04917_x vsd CPUCON1 CPUCON2 CSP IP Return Stack FIFO Branch Unit Prefetch Unit VECSEG TFR IDX0 IDX1 ...

Page 143: ...ltaneously at least two instructions via a 64 bit wide bus from the Program Management Unit PMU The prefetched instructions are stored in an instruction FIFO Preprocessing of branch instructions enables the instruction flow to be predicted While the CPU is in the process of executing an instruction fetched from the FIFO the prefetcher of the IFU starts to fetch a new instruction at a predicted tar...

Page 144: ...The target address is also used to prefetch the next instructions For the Processing Pipeline both instructions are fetched from the FIFO again and are executed in parallel If the instruction flow was predicted incorrectly or FIFO is empty the two stages of the IFU can be bypassed Note Pipeline behavior in case of a incorrectly predicted instruction flow is described in the following sections MCA0...

Page 145: ...refetcher is able to fetch more instructions than the processing pipeline can execute In Tn 4 the FIFO and prefetch buffer are filled and no further instructions can be prefetched The PMU address stays Table 4 1 Branch Classes and Prediction Rules Branch Instruction Classes Instructions Prediction Rule Assumption Inter segment branch instructions JMPS seg caddr CALLS seg caddr The branch is always...

Page 146: ...REFETCH 96 bit Buffer In 6 In 9 In 9 In 11 In 12 In 13 In 14 In 15 In 15 In 19 In 15 In 19 In 16 In 19 In 17 In 19 In 18 In 21 FETCH Instruction Buffer In 5 In 6 In 7 In 8 In 9 In 10 In 11 In 12 In 13 In 14 In 15 In 16 In 17 FIFO contents In 3 In 5 In 4 In 8 In 5 In 11 In 6 In 13 In 7 In 14 In 7 In 14 In 8 In 15 In 9 In 16 In 10 In 17 Fetch from FIFO In 4 In 5 In 6 In 7 In 7 In 8 In 9 In 10 In 11 ...

Page 147: ... 1 which delivers the first data in the next cycle Tn 2 But the target instruction crosses the 64 bit memory boundary and a second fetch in Tn 3 is required to get the entire 32 bit instruction In Tn 4 the Prefetch Buffer contains two 32 bit instructions while the first instruction Im is directly forwarded to the Decode stage The prefetcher is now restarted and prefetches further instructions In T...

Page 148: ...a Ia 8 Ia 16 Ia 24 I I I I PMU Data 64bit I Id Id 1 Id 2 Id 3 I I I PREFETCH 96 bit Buffer I Im Im 1 Im 2 Im 3 Im 4 Im 5 I I FETCH Instruction Buffer Inext 2 Im 1 Im 2 Im 3 Im 4 Im 5 I Fetch from FIFO Im 3 Im 4 Im 5 DECODE Inext 1 Im Im 1 Im 2 Im 3 Im 4 ADDRESS Inext Im Im 1 Im 2 Im 3 MEMORY Ibranch Im Im 1 Im 2 EXECUTE In Ibranch Im Im 1 WRITE BACK In Ibranch Im MCA04919 I Im 5 Im 5 Im 4 Im 4 Im ...

Page 149: ...LU or MAC Unit operation is performed on the previously fetched operands The condition flags are updated All explicit write operations to CPU SFRs and all auto increment auto decrement operations of GPRs used as indirect address pointers are performed 7th WRITE BACK All external operands and the remaining operands within the internal DPRAM space are written back Operands located in the internal SR...

Page 150: ...peline requires attention by the programmer In these cases the delays caused by the pipeline conflicts can be used for other instructions to optimize performance Note The XC2200 has a fully interlocked pipeline which means that these conflicts do not cause any malfunction Instruction re ordering is only required for performance reasons The following examples describe the pipeline behavior in speci...

Page 151: ...on of instructions without any delay despite of data dependencies Conflict_GPRs_Resolved In ADD R0 R1 Compute new value for R0 In 1 ADD R3 R0 Use R0 again In 2 ADD R6 R0 Use R0 again In 3 ADD R6 R1 Use R6 again In 4 Table 4 4 Resolved Pipeline Dependencies Using GPRs Stage Tn Tn 1 Tn 2 Tn 3 1 1 R0 forwarded from EXECUTE to MEMORY Tn 4 2 2 R0 forwarded from WRITE BACK to MEMORY Tn 5 3 3 R6 forwarde...

Page 152: ...ss stage Conflict_GPRs_Pointer_Stall In ADD R0 R1 Compute new value for R0 In 1 MOV R3 R0 Use R0 as address pointer In 2 ADD R6 R0 In 3 ADD R6 R1 In 4 Table 4 5 Pipeline Dependencies Using GPRs as Pointers Stall Stage Tn Tn 1 Tn 2 1 1 New value of R0 not yet available Tn 3 2 2 R0 forwarded from EXECUTE to ADDRESS next cycle Tn 4 Tn 5 DECODE In ADD R0 R1 In 1 MOV R3 R0 In 2 In 2 In 2 In 3 ADDRESS I...

Page 153: ...ry table has one entry for each of the GPRs The entries store the information of the last accessed memory area using the corresponding GPR In the case of an incorrect prediction of the memory area the read access must be restarted It is recommended that the GPRs used for indirect addressing always point to the same memory area If an updated GPR points to a different memory area the next read opera...

Page 154: ...R3 R0 In 1 MOV R0 R4 In 2 In 3 In 4 MEMORY In 2 In 1 In ADD R3 R0 In 1 MOV R0 R4 In 2 In 3 EXECUTE In 3 In 2 In 1 In ADD R3 R0 In 1 MOV R0 R4 In 2 WR BACK In 4 In 3 In 2 In 1 In ADD R3 R0 In 1 MOV R0 R4 Table 4 8 Pipeline Dependencies with Pointers Invalid Speculation Stage Tm Tm 1 Tm 2 1 1 Access to location R0 must be repeated due to wrong history target area was changed Tm 3 Tm 4 Tm 5 DECODE Im...

Page 155: ...fer until read accesses are finished All instructions except the CoXXX instructions can read only one memory operand per cycle A conflict between the read and one write access cannot occur because the DPRAM has two independent read write ports Only other pipeline stall conditions can generate a DPRAM bandwidth conflict The DPRAM is a synchronous pipelined memory The read access starts with the val...

Page 156: ... the DSRAM to guarantee a single cycle execution of the CoXXX instructions Conflict_DPRAM_Bandwidth In ADD op1 R1 In 1 ADD R6 R0 In 2 CoMAC IDX0 R0 In 3 MOV R3 R0 In 4 Table 4 9 Pipeline Dependencies in Case of Memory Conflicts DPRAM Stage Tn Tn 1 Tn 2 Tn 3 Tn 4 1 1 COMAC instruction stalls due to memory bandwidth conflict Tn 5 DECODE In ADD op1 R1 In 1 ADD R6 R0 In 2 CoMAC In 3 MOV R3 R0 In 4 In ...

Page 157: ...ack Conflict_DSRAM_Bandwidth In ADD op1 R1 In 1 ADD R6 R0 In 2 ADD R6 op2 In 3 MOV R3 R2 In 4 Table 4 10 Pipeline Dependencies in Case of Memory Conflicts DSRAM Stage Tn Tn 1 Tn 2 Tn 3 Tn 4 1 1 ADD R6 op2 instruction stalls due to memory bandwidth conflict Tn 5 DECODE In ADD op1 R1 In 1 ADD R6 R0 In 2 ADD R6 op2 In 3 MOV R3 R2 In 4 In 4 ADDRESS In 1 In ADD op1 R1 In 1 ADD R6 R0 In 2 ADD R6 op2 In ...

Page 158: ...cases and stalls the pipeline to guarantee a correct execution For performance reasons the CPU differentiates between different classes of CPU SFRs The flow of instructions through the pipeline can be improved by following the given rules used for instruction re ordering There are three classes of CPU SFRs CSFRs not generating pipeline conflicts ONES ZEROS MCW CSFR result registers updated late in...

Page 159: ...ndencies with Result CSFRs Stall Stage Tn Tn 1 Tn 2 Tn 3 1 1 Cannot read MDL here Tn 4 Tn 5 DECODE In MUL R0 R1 In 1 MOV R6 MDL In 2 ADD R6 R1 In 3 MOV R3 R0 In 3 MOV R3 R0 In 4 ADDRESS In 1 In MUL R0 R1 In 1 MOV R6 MDL In 2 ADD R6 R1 In 2 ADD R6 R1 In 3 MOV R3 R0 MEMORY In 2 In 1 In MUL R0 R1 In 1 MOV R6 MDL In 1 MOV R6 MDL In 2 ADD R6 R1 EXECUTE In 3 In 2 In 1 In MUL R0 R1 In 1 MOV R6 MDL WR BAC...

Page 160: ...ADD R6 R1 In 4 Table 4 12 Pipeline Dependencies with Result CSFRs No Stall Stage Tn Tn 1 Tn 2 Tn 3 Tn 4 1 1 MDL can be read now no stall cycle necessary Tn 5 DECODE In MUL R0 R1 In 1 MOV R3 R0 In 2 MOV R6 MDL In 3 ADD R6 R1 In 4 In 5 ADDRESS In 1 In MUL R0 R1 In 1 MOV R3 R0 In 2 MOV R6 MDL In 3 ADD R6 R1 In 4 MEMORY In 2 In 1 In MUL R0 R1 In 1 MOV R3 R0 In 2 MOV R6 MDL In 3 ADD R6 R1 EXECUTE In 3 ...

Page 161: ... in the following list are held in the DECODE stage all other instructions are not held Instructions using long addressing mode mem Instructions using indirect addressing modes Rw Rw except JMPI and CALLI ENWDT DISWDT EINIT All CoXXX instructions If the CPUCON1 CP SP STKUN STKOV VECSEG TFR or the PSW are modified and the instruction_modify_CSFR reaches the EXECUTE stage the pipeline is canceled Th...

Page 162: ... mem In 1 MOV R6 mem In 2 ADD R6 R1 ADDRESS In 1 In MOV IDX1 12 In 1 MOV R6 mem MEMORY In 2 In 1 In MOV IDX1 12 EXECUTE In 3 In 2 In 1 In MOV IDX1 12 WR BACK In 4 In 3 In 2 In 1 In MOV IDX1 12 Table 4 14 Pipeline Dependencies with Control CSFRs Optimized Stage Tn Tn 1 Tn 2 Tn 3 Tn 4 Tn 5 DECODE In MOV IDX1 12 In 1 MOV MAH 23 In 2 MOV MAL 25 In 3 MOV R3 08 In 4 In 5 ADDRESS In 1 In MOV IDX1 12 In 1...

Page 163: ...ESS and DECODE Stage are stalled If the instruction reaches the EXECUTE stage the entire pipeline and the Instruction FIFO of the IFU are canceled The instruction flow is completely re started Conflict_Canceling_Completely In MOV PSW R4 In 1 MOV R6 R1 In 2 ADD R6 R1 In 3 MOV R3 R0 In 4 Table 4 15 Pipeline Dependencies with Control CSFRs Cancel All Stage Tn 1 Tn 2 Tn 3 Tn 4 Tn 5 Tn 6 DECODE In 1 MO...

Page 164: ...e 00 Space between two vectors is 2 words1 01 Space between two vectors is 4 words 10 Space between two vectors is 8 words 11 Space between two vectors is 16 words 1 The default value 2 words is compatible with the vector distance defined in the C166 Family architecture WDTCTL 4 rw Configuration of Watchdog Timer 0 DISWDT executable only until End Of Init2 1 DISWDT ENWDT always executable enhanced...

Page 165: ...r cycle 10 FIFO filled with up to two instructions per cycle 11 FIFO filled with up to three instruction per cycle BYPPF 9 rw Prefetch Bypass Control 0 Bypass path from prefetch to decode disabled 1 Bypass path from prefetch to decode available BYPF 8 rw Fetch Bypass Control 0 Bypass path from fetch to decode disabled 1 Bypass path from fetch to decode available EIOIAEN 7 rw Early IO Injection Ack...

Page 166: ...hese registers must not be modified by application software exceptions will be documented e g in an errata sheet OVRUN 4 rw Pipeline Control 0 Overrun of pipeline bubbles not allowed 1 Overrun of pipeline bubbles allowed RETST 3 rw Enable Return Stack 0 Return Stack is disabled 1 Return Stack is enabled DAID 1 rw Disable Atomic Injection Deny 0 Injection requests are denied during Atomic 1 Injecti...

Page 167: ...anks are accessed via the 5 port register file providing the high access speed required for the CPU s performance The register file is split into three independent physical register banks There are two types of register banks Two local register banks which are a part of the register file A global register bank which is memory mapped and cached in the register file Figure 4 5 Register File R15 MCD0...

Page 168: ... register bank represents a cache The banks of the memory mapped GPRs global bank are located in the internal DPRAM One bank uses a block of 16 consecutive words A Context Pointer CP register determines the base address of the current selected bank To provide the required access speed the GPRs located in the DPRAM are cached in the 5 port register file only one memory mapped GPR bank can be cached...

Page 169: ...ccesses are possible in this way Note GPRs used as indirect address pointers are always accessed wordwise For the local register banks the resulting offset is used directly for the global register bank the resulting offset is logically added to the contents of register CP which points to the memory location of the base of the current global register bank see Figure 4 7 Short 8 Bit Register Address...

Page 170: ...n into the global register bank without further delay MOV mem R4 Note The 24 bit GPR addressing mode is not recommended because it requires an extra cycle for the read and write access Table 4 16 Addressing Modes to Access GPRs Word Registers1 1 The first 8 GPRs R7 R0 may also be accessed bytewise Writing to a GPR byte does not affect the other byte of the respective GPR Byte Registers Short Addre...

Page 171: ...he bank switch can be automatically executed by updating bitfield BANK from registers BNKSELx in the interrupt controller By executing a RETI instruction bitfield BANK will automatically be restored and the context will switched to the original register bank The switch between the three physical register banks of the register file can also be executed by writing to bitfield BANK Because of pipelin...

Page 172: ...uring the validation process The way the validation process is completed depends on the type of register bank selected for this interrupt If the interrupt also uses a global register bank the validation process is finished before executing the service routine see Figure 4 9 If the interrupt uses a local register bank the validation process is interrupted and the service routine is executed immedia...

Page 173: ...ution Task A Global Bank Global Bank Global Bank Finished Register Bank Validation Process Started Execution of SCXT CP Execution of POP CP MCA04875 Stopped Register Bank Validation Process Started Execution of SCXT CP Interrupt of Task B recognized Execution of RETI Execution Task A Execution Task B Execution Task A Global Bank Local Bank Global Bank Finished Register Bank Validation Process Rest...

Page 174: ...ointer CP into the system stack and loads CP with the immediate value New_Bank which selects a new register bank The service routine may now use its own registers This memory register bank is preserved when the service routine terminates i e its contents are available on the next call Before returning from the service routine RETI the previous CP is simply popped from the system stack which return...

Page 175: ...lects the code segment being used at run time to access instructions The lower 8 bits of register CSP select one of up 256 segments of 64 Kbytes each while the higher 8 bits are reserved for future use The reset value is specified by the contents of the VECSEG register Section 5 3 Note Register CSP can only be read but cannot be written by data operations In segmented memory mode default after res...

Page 176: ...rently fetched instruction within the code segment selected by the CSP register Register IP is not mapped into the XC2200 s address space thus it is not directly accessible by the programmer However the IP can be modified indirectly via the stack by means of a return instruction IP is implicitly updated by the CPU for branch instructions and after instruction fetch operations CSP Code Segment Poin...

Page 177: ...ong indirect for word byte and bit data accesses The different addressing modes use different formats and have different scopes 4 7 1 Short Addressing Modes Short addressing modes allow access to the GPR SFR or bit addressable memory space All of these addressing modes use an offset 8 4 2 bits together with an implicit base address to specify a 24 bit physical address Table 4 17 Short Addressing M...

Page 178: ...d ESFR area The reg accesses to the ESFR area require a preceding EXT R instruction to switch the base address Depending on the opcode either the total word for word operations or the low byte for byte operations of an SFR can be addressed via reg Note that the high byte of an SFR cannot be accessed via the reg addressing mode Short reg addresses in the range from F0H to FFH always specify GPRs In...

Page 179: ...4 bit data page offset see Figure 4 13 Select the used data page directly The data page is selected by a preceeding EXTP R instruction bits 13 0 of the used 16 bit pointer specify the 14 bit data page offset Select the used segment directly The segment is selected by a preceeding EXTS R instruction the used 16 bit pointer specifies the 16 bit segment offset Note Word accesses on odd byte addresses...

Page 180: ...n in Figure 4 13 If the user does not want to use data paging no further action is required Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DPP register selected by the upper two bits of the 16 bit address The contents of the selected DPP register specify one of the 1024 possible data pages This data page base addres...

Page 181: ...g the DPP Mechanism Note The overriding page or segment may be specified as a constant pag seg or via a word GPR Rw Table 4 18 Long Addressing Modes Mnemonic Base Address1 1 Represents either a 10 bit data page number to be concatenated with a 14 bit offset or an 8 bit segment number to be concatenated with a 16 bit offset Offset Scope of Access mem DPPx mem 3FFFH Any Word or Byte mem pag mem 3FFF...

Page 182: ...t case The following indirect addressing modes are provided Table 4 19 Generating Physical Addresses from Indirect Pointers Step Executed Action Calculation Notes 1 Calculate the address of the indirect pointer word GPR from its short address GPR Address 2 Short Addr CP see Table 4 17 2 Pre decrement indirect pointer Rw depending on datatype 1 or 2 for byte or word operations GPR Address GPR Addre...

Page 183: ...ly pre decremented by 2 or 1 for word or byte data operations before the access Rw data16 The specified 16 bit constant is added to the indirect address pointer before the long address is calculated Rw The specified indirect address pointer is automatically post decremented by 2 word data operations after the access Rw QRx The specified indirect address pointer is automatically post incremented by...

Page 184: ...dress pointers can be used for arithmetic operations as well as for the special CoMOV instruction The generation of the 24 bit memory address is different For CoMOV instructions the IDX pointers are concatenated with the DPPs or the selected page segment address as described for long addressing modes see Figure 4 13 for a summary For arithmetic CoXXX instructions the IDX pointers are automatically...

Page 185: ...ress pointers IDXx contents by 2 or by the contents of the offset registers QX0 and QX1 used in conjunction with the IDX pointers Note During the initialization of the QX registers instruction flow stalls are possible For the proper operation refer to Section 4 3 4 QX0 Offset Register ESFR F000H 00H Reset Value 0000H QX1 Offset Register ESFR F002H 01H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 ...

Page 186: ...set registers QXx Interm Addr IDXx Address Optional step executed only if required by instruction CoXXXM and addressing mode 3 Calculate long 16 bit address Long Address IDXx Pointer 4 Calculate the physical 24 bit address using the resulting pointer Physical Addr Page Segment Pointer offset Uses DPPs or page segment override mechanisms see Table 4 18 and Figure 4 15 5 Post in decrement indirect p...

Page 187: ...instruction the address stored in the specified indirect address pointer is automatically pre incremented by 2 for the parallel move operation The pointer itself is not pre incremented Then the specified indirect address pointer is automatically post decremented by 2 after the access IDXx QXx The specified indirect address pointer is automatically post incremented by QXx after the access with para...

Page 188: ...n Table 4 23 The example in Figure 4 16 shows the complex operation of CoXXXM instructions with a parallel move operation based on the descriptions about addressing modes given in Section 4 7 3 Indirect Addressing Modes and Section 4 7 4 DSP Addressing Modes Table 4 23 Coding of the CoREG Addressing Mode Mnemonic Register Coding of wwww w bits 31 27 MSW MAC Unit Status Word 00000 MAH MAC Unit Accu...

Page 189: ...rmediate Address IDX0 2 3 Calculate Long 16 Bit Address Long Address 1 IDX0 Long Address 2 R2 4 Calculate 24 Bit Physical Address Physical Address 1 Page 3 Page Offset Physical Address 2 DPPi Page Offset 5 Post Modify Address Pointer IDX0 new IDX0 2 R2 new R2 2 Data Operations 1 Read Operands op1 Physical Address 1 op2 Physical Address 2 1 Write Operand op1 Intermediate Address op1 CoXXXMxx IDX0 R...

Page 190: ... bitaddressable selects the segment being used at run time to access the system stack The lower eight bits of register SPSEG select one of up 256 segments of 64 Kbytes each while the higher 8 bits are reserved for future use The Stack Pointer SP not bitaddressable points to the top of the system stack TOS SP is pre decremented whenever data is pushed onto the stack and it is post incremented whene...

Page 191: ...P can use the new value Extreme care should be taken when changing the contents of the stack pointer registers Improper changes may result in erroneous system behavior SP Stack Pointer Register SFR FE12H 09H Reset Value FC00H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sp 0 rwh r Field Bits Type Description sp 15 1 rwh Modifiable Portion of Register SP Specifies the top of the system stack SPSEG Stack P...

Page 192: ...k may have been overwritten by the status information stacked upon servicing the trap itself Virtual stack control allows the system stack to be used as a Stack Cache for a bigger external user stack flush cache in case of an overflow refill cache in case of an underflow Scope of Stack Limit Control The stack limit control implemented by the register pair STKOV and STKUN detects cases in which the...

Page 193: ...rw Field Bits Type Description stkov 15 1 rw Modifiable Portion of Register STKOV Specifies the segment offset address of the lower limit of the system stack STKUN Stack Underflow Reg SFR FE16H 0BH Reset Value FC00H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stkun 0 rw r Field Bits Type Description stkun 15 1 rw Modifiable Portion of Register STKUN Specifies the segment offset address of the upper limi...

Page 194: ... by the user selectable branch test The status flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine Another group of bits represents the current CPU interrupt status Two separate bits USR0 and USR1 are provided as general purpose flags PSW Processor Status Word SFR Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN HLD EN BANK USR 1 USR 0 MUL...

Page 195: ...ediately preceding instruction Note After reset all of the ALU status bits are cleared N Flag For most of the ALU operations the N flag is set to 1 if the most significant bit of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N 1 positive N 0 USR1 7 rwh General Purpose Flag May be used by applic...

Page 196: ...itize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag represents the logical ANDing of the two specified bits V Flag For addition subtraction and 2 s complementation the V flag is always set to 1 if the result exceeds...

Page 197: ...ot If the value of the source operand of an instruction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000H for the word data type or 80H for the byte data type the E flag is set to 1 otherwise it is cleared General Control Functions USR0 USR1 BANK HLDEN A few bits in register PSW are dedicated to general control functions Thus they ar...

Page 198: ...r provides multiple bit shifts in a single cycle Rotations and arithmetic shifts are also supported 4 8 2 Bit Manipulation Unit The XC2200 offers a large number of instructions for bit processing These instructions either manipulate software flags within the internal RAM control on chip peripherals via control bits in their respective SFRs or control IO functions via port pins Unlike other microco...

Page 199: ...rea ESFR area and internal DPRAM are bit addressable so the register bits located within those respective sections can be manipulated directly using bit instructions The other SFRs must be accessed byte word wise Note All GPRs are bit addressable independently from the allocation of the register bank via the Context Pointer CP Even GPRs which are allocated to non bit addressable RAM locations prov...

Page 200: ...is finished To avoid these stalls the multiply and division unit should not be used during the first fourteen CPU cycles of the interrupt tasks For example this requires up to fourteen one cycle instructions to be executed between the interrupt entry and the first instruction which uses the multiply and divide unit again worst case Multiplications and divisions implicitly use the 32 bit multiply d...

Page 201: ... be saved prior to a new multiplication or division operation MDL Multiply Divide Low Reg SFR FE0EH 07H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mdl rwh Field Bits Type Description mdl 15 0 rwh Low Part of MD The low order sixteen bits of the 32 bit multiply and divide register MD MDC Multiply Divide Control Reg SFR FF0EH 87H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M...

Page 202: ...includes the following major components shown in Figure 4 18 16 bit by 16 bit signed unsigned multiplier with signed result1 Concatenation Unit Scaler one bit left shifter for fractional computing 40 bit Adder Subtracter 40 bit Signed Accumulator Data Limiter Accumulator Shifter Repeat Counter Figure 4 18 Functional MAC Unit Block Diagram 1 The same hardware multiplier is used in the ALU MCA04930 ...

Page 203: ...he sign bit is the MSB of the binary word This is set to zero for positive numbers and set to one for negative numbers Unsigned numbers are supported only by multiply multiply accumulate instructions which specify whether each operand is signed or unsigned In 2 s complement fractional format the N bit operand is represented using the 1 N 1 format 1 signed bit N 1 fractional bits Such a format can ...

Page 204: ...nation or by control bit MP in register MCW If bit MP is set the product is shifted one bit to the left to compensate for the extra sign bit gained in multiplying two 16 bit 2 s complement numbers The enabled automatic shift is performed only if both input operands are signed 4 9 6 The 40 bit Adder Subtracter The 40 bit Adder Subtracter allows intermediate overflows in a series of multiply accumul...

Page 205: ... Shifter The accumulator shifter is a parallel shifter with a 40 bit input and a 40 bit output The source accumulator shifting operations are No shift Unmodified Up to 16 bit Arithmetic Left Shift Up to 16 bit Arithmetic Right Shift Notice that bits ME MSV and MSL in register MSW are affected by left shifts therefore if the saturation mechanism is enabled MS the behavior is similar to the one of t...

Page 206: ...s complement notation One may see that the extended 40 bit value is equal to the 32 bit value without extension In other words after this extension MAE does not contain significant bits Generally this condition is present when the highest 9 bits of the 40 bit signed result are the same During the accumulator operations an overflow may happen and the result may not fit into 32 bits and MAE will cha...

Page 207: ...4 69 V2 1 2008 08 CPUSV2_X V2 2 MAH Accumulator High Word SFR FE5EH 2FH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAH rwh Field Bits Type Description MAH 15 0 rwh High Part of Accumulator The 40 bit accumulator is completed by the accumulator low word MAL and bitfield MAE ...

Page 208: ...wh rwh rwh rwh rwh rwh rwh Field Bits Type Description MV 14 rwh Overflow Flag 0 No Overflow produced 1 Overflow produced MSL 13 rwh Sticky Limit Flag 0 Result was not saturated 1 Result was saturated ME 12 rwh MAC Extension Flag 0 MAE does not contain significant bits 1 MAE contains significant bits MSV 11 rwh Sticky Overflow Flag 0 No Overflow occurred 1 Overflow occurred MC 10 rwh Carry Flag 0 ...

Page 209: ...F FFFFH MZ Flag The MZ flag is normally set to 1 if the result of a MAC operation equals zero otherwise it is cleared MC Flag After a MAC addition the MC flag indicates that a Carry from the most significant bit of the accumulator extension MAE has been generated After a MAC subtraction or a MAC comparison the MC flag indicates a Borrow representing the logical negation of a Carry for the addition...

Page 210: ...at if the MV flag indicates an arithmetic overflow the result of the integer addition integer subtraction or accumulation is not valid 4 9 11 The Repeat Counter MRW The Repeat Counter MRW controls the number of repetitions a loop must be executed The register must be pre loaded before it can be used with USRx CoXXX operations MAC operations are able to decrement this counter When a USRx CoXXX inst...

Page 211: ...ed the MRW counter is decremented MOV MRW 19 Pre load loop counter loop01 USR1 CoMACM IDX0 R0 Calculate and decrement MSW ADD R2 0002H JMPA cc_nusr1 loop01 Repeat loop until USR1 is set Note Because correctly predicted JMPA is executed in 0 cycle it offers the functionality of a repeat instruction Table 4 26 Encoding of MAC Repeat Word Control Code in rrr Effect on Repeat Counter 000B regular CoXX...

Page 212: ...ample for bit manipulation or mask generation The constant registers can be accessed via any instruction capable of addressing an SFR ZEROS Zeros Register SFR FF1CH 8EH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r Field Bits Type Description 0 15 0 r Constant Zero Bit ONES Ones Register SFR FF1EH 8FH Reset Value FFFFH 15 14...

Page 213: ...C Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two locations through one of eight programmable PEC Service Channels During a PEC transfer normal program execution of the CPU is halted No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing Trap Functions ...

Page 214: ... This allows direct identification of the source which caused the request The Class B hardware traps all share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The res...

Page 215: ...ral Event Controller PEC Arbitration Interrupt Handler Interrupt Request Request Control EOP INT 2 Arbitr Winner Interrupt Request Request Control Injection Control CPU Action Request PEC Request irq n 1 SRCP1 SRCP0 SRCP7 DSTP1 DSTP0 DSTP7 PECSEG1 PECSEG0 PECSEG7 PEC Pointer Interrupt and Peripheral Event Controller irq n 2 1 irq n 3 irq0 irq1 irq2 irq3 Interrupt Request Lines C166S V2 CPU Injecti...

Page 216: ... request sets the associated interrupt request flag xxIR If the requesting interrupt node is enabled by the associated interrupt enable bit xxIE arbitration starts with the next clock cycle or after completion of an arbitration cycle that is already in progress All interrupt requests pending at the beginning of a new arbitration cycle are considered independently from when they were actually reque...

Page 217: ...compares the winner s 4 bit priority level disregarding the group level with the 5 bit OCDS service request priority The 4 bit ILVL of the interrupt request is extended to a 5 bit value with MSB 0 This means that any OCDS request with MSB 1 will always win the second stage arbitration However if there is a conflict between an OCDS request and an interrupt request the interrupt request wins The Thi...

Page 218: ...lete interrupt control and status information of the associated source required during one round of prioritization arbitration cycle the upper 7 bits are reserved for future use All interrupt control registers are bit addressable and all bits can be read or written via software Therefore each interrupt source can be programmed or modified with just one instruction xxIC Interrupt Control Register E...

Page 219: ...s part in the arbitration process enabled or not disabled The associated request flag will be set upon a source request in any case The occurrence of an interrupt request can so be polled via xxIR even while the node is disabled Note In this case the interrupt request flag xxIR is not cleared automatically but must be cleared via software Interrupt Priority Level and Group Level The four bits of b...

Page 220: ... the operation of the CPU This bitfield reflects the priority level of the routine currently executed Upon entry into an interrupt service routine this bitfield is updated with the priority level of the request being serviced The PSW is saved on the system stack before the request is serviced The CPU level determines the minimum interrupt priority level which will be serviced Any request on the sa...

Page 221: ... time critical code sequences Interrupt requests in the XC2200 can be disabled and enabled on three different levels Control all interrupt requests globally Control configurable groups of interrupt requests Control single interrupt requests Global interrupt control is achieved with a single instruction BCLR IEN Clear IEN flag causes pipeline restart Groups of interrupts classes are defined and con...

Page 222: ...inue GlobalIntOff Interrupts are globally disabled anyway BCLR T2IE Disable Timer 2 interrupt node JNB T2IE Continue Reading T2IC can be omitted if the next Continue few instructions do not set IEN The same function can easily be implemented as a C macro define Disable_One_Interrupt IE_bit if IEN IEN 0 IE_bit 0 while IE_bit IEN 1 else IE_bit 0 while IE_bit Usage Example Disable_One_Interrupt T2IE ...

Page 223: ...or locations build a vector table located in the address space of the XC2200 The vector table usually contains the appropriate jump instructions that transfer control to the interrupt or trap service routines These routines may be located anywhere within the address space The location and organization of the vector table is programmable The Vector Segment register VECSEG defines the segment of the...

Page 224: ...ions This is required because the vector table also provides the reset vector VECSEG Vector Segment Pointer SFR FF12H 89H Reset Value Table 5 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vecseg rwh Field Bits Type Description vecseg 7 0 rwh Segment number of the Vector Table Table 5 1 Reset Values for Register VECSEG Initial Value Reset Configuration 0000H Standard start from external memory 00C0H Stan...

Page 225: ... USIC0 Request 7 CC2_CC21IC xx 0054H 15H 21D CAPCOM Register 22 or USIC1 Request 6 CC2_CC22IC xx 0058H 16H 22D CAPCOM Register 23 or USIC1 Request 7 CC2_CC23IC xx 005CH 17H 23D CAPCOM Register 24 or ERU Request 0 CC2_CC24IC xx 0060H 18H 24D CAPCOM Register 25 or ERU Request 1 CC2_CC25IC xx 0064H 19H 25D CAPCOM Register 26 or ERU Request 2 CC2_CC26IC xx 0068H 1AH 26D CAPCOM Register 27 or ERU Reque...

Page 226: ... Request 7 ADC_7IC xx 00BCH 2FH 47D CCU60 Request 0 CCU60_0IC xx 00C0H 30H 48D CCU60 Request 1 CCU60_1IC xx 00C4H 31H 49D CCU60 Request 2 CCU60_2IC xx 00C8H 32H 50D CCU60 Request 3 CCU60_3IC xx 00CCH 33H 51D CCU61 Request 0 CCU61_0IC xx 00D0H 34H 52D CCU61 Request 1 CCU61_1IC xx 00D4H 35H 53D CCU61 Request 2 CCU61_2IC xx 00D8H 36H 54D CCU61 Request 3 CCU61_3IC xx 00DCH 37H 55D CCU62 Request 0 CCU6...

Page 227: ... Request 14 CAN_14IC xx 0138H 4EH 78D CAN Request 15 CAN_15IC xx 013CH 4FH 79D USIC0 Request 0 U0C0_0IC xx 0140H 50H 80D USIC0 Request 1 U0C0_1IC xx 0144H 51H 81D USIC0 Request 2 U0C0_2IC xx 0148H 52H 82D USIC0 Request 3 U0C1_0IC xx 014CH 53H 83D USIC0 Request 4 U0C1_1IC xx 0150H 54H 84D USIC0 Request 5 U0C1_2IC xx 0154H 55H 85D USIC1 Request 0 U1C0_0IC xx 0158H 56H 86D USIC1 Request 1 U1C0_1IC xx...

Page 228: ...01A0H 68H 104D Unassigned node xx 01A4H 69H 105D Unassigned node xx 01A8H 6AH 106D SCU Request 1 SCU_1IC xx 01ACH 6BH 107D SCU Request 0 SCU_0IC xx 01B0H 6CH 108D Program Flash Modules PFM_IC xx 01B4H 6DH 109D RTC RTC_IC xx 01B8H 6EH 110D End of PEC Subchannel EOPIC xx 01BCH 6FH 111D 1 Register VECSEG defines the segment where the vector table is located to Bitfield VECSC in register CPUCON1 defin...

Page 229: ...a the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests Table 5 3 Hardware Trap Summary Exception Condition Trap Flag Trap Vector Vector Location1 1 Register VECSEG defines the segment where the vector table is located to Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors This table represents the default setting...

Page 230: ... sources on priority levels 15 12 The two pointers are each stored in a pair of interrupt jump table cache registers FINTxADDR FINTxCSP which store a pointer s segment and offset along with the priority level it shall be assigned to select the same priority that is programmed for the respective interrupt node FINT0ADDR Fast Interrupt Address Reg 0 XSFR EC02H Reset Value 0000H FINT1ADDR Fast Interr...

Page 231: ...with bitfield GLVL ILVL 11 10 rw Interrupt Priority Level This selects the interrupt priority 15 12 of the request this pointer shall be assigned to 00 Interrupt priority level 12 1100B 01 Interrupt priority level 13 1101B 10 Interrupt priority level 14 1110B 11 Interrupt priority level 15 1111B GLVL 9 8 rw Group Priority Level Together with bit GPX this selects the group priority of the request t...

Page 232: ...tion of block transfers 5 4 1 The PECC Registers The PECC registers control the action performed by the respective PEC channel Transfer Size bit BWT controls whether a byte or a word is moved during a PEC service cycle This selection controls the transferred data size and the increment step for the pointer s to be modified Pointer Modification bitfield INC controls which of the PEC pointers is inc...

Page 233: ...ly 1B Pairs of PEC channels are linked together1 1 For a functional description see Channel Link Mode for Data Chaining INC 10 9 rw Increment Control Pointer Modification 2 00B Pointers are not modified 01B Increment DSTPx by 1 or 2 BWT 1 or 0 10B Increment SRCPx by 1 or 2 BWT 1 or 0 11B Increment both DSTPx and SRCPx by 1 or 2 2 Pointers are incremented decremented only within the current segment...

Page 234: ...nnel group 3 0 with PLEV 10B The actual PEC channel number is then determined by the group priority levels 3 0 i e GPX 0 Simultaneous requests for PEC channels are prioritized according to the PEC channel number where channel 0 has lowest and channel 7 has highest priority Note All sources requesting PEC service must be programmed to different PEC channels Otherwise an incorrect PEC channel may be...

Page 235: ... 0 1 1 CPU interrupt level 15 group prio 3 PEC service channel 7 CPU interrupt level 15 group prio 3 1 1 1 1 0 1 0 CPU interrupt level 15 group prio 2 PEC service channel 6 CPU interrupt level 15 group prio 2 1 1 1 0 0 1 0 CPU interrupt level 14 group prio 2 PEC service channel 2 CPU interrupt level 14 group prio 2 1 1 0 1 1 1 0 CPU interrupt level 13 group prio 6 CPU interrupt level 13 group prio...

Page 236: ... Thus a pointer may be incremented within the current segment but may not cross the segment boundary When a PEC pointer reaches the maximum offset FFFEH for word transfers FFFFH for byte transfers it is not incremented further but keeps its maximum offset value This protects memory in adjacent segments from being overwritten unintentionally No explicit error event is generated by the system in cas...

Page 237: ... 7 PEC Destination Pointer x XSFR EC42H 4 x Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSTPx rwh Field Bits Type Description DSTPx 15 0 rwh Destination Pointer Offset of Channel x Destination address bits 15 0 PECSEGx x 0 7 PEC Segment Pointer x XSFR EC80H 2 x Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRCSEGx DSTSEGx rw rw Field Bits Type Description SRCSEGx 15 8 rw Sour...

Page 238: ... PEC channel action depend on the previous contents of COUNT Table 5 7 PEC Data Pointer Register Addresses Channel 0 1 2 3 4 5 6 7 PECSEGx EC80H EC82H EC84H EC86H EC88H EC8AH EC8CH EC8EH SRCPx EC40H EC44H EC48H EC4CH EC50H EC54H EC58H EC5CH DSTPx EC42H EC46H EC4AH EC4EH EC52H EC56H EC5AH EC5EH Table 5 8 Influence of Bitfield COUNT Previous COUNT Modified COUNT IR after Service Action of PEC Channe...

Page 239: ...s cleared to indicate that the request has been serviced When COUNT contains the value 00H the respective PEC channel remains idle and the associated interrupt service routine is activated instead This allows servicing requests on all priority levels by standard interrupt service routines Continuous transfers are selected by the value FFH in bitfield COUNT In this case COUNT is not modified and th...

Page 240: ...nking is executed if the active channel s link control bit CL is 1 at the time its transfer count decrements from 1 to 0 count 0 before and the transfer count of the other channel is non zero In this case the active channel issues an EOP interrupt request and the respective other channel of the pair is automatically selected Note Channel linking always begins with the even channel Channel linking ...

Page 241: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw rwh rw Field Bits Type Description CxIR x 0 7 2 x 1 rwh Interrupt Request Flag of PEC Channel x 0B No request from PEC channel x pending 1B PEC channel x has raised an end of PEC interrupt request Note These request flags must be cleared by ...

Page 242: ...upt service routine must service and clear all currently active requests before terminating Requests occurring later will set EOPIR again and the service routine will be re entered MCD04914 C7IR C7IE C6IR C6IE C5IR C5IE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE C0IR C0IE 1 PECISNC 15 0 0 0 0 0 0 0 0 GPX EOP IR EOP IE ILVL GLVL 15 8 7 0 EOPIC Interrupt Request Pulse Generator ...

Page 243: ...he source is serviced only if its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or a lower level An interrupt source assigned to level 0 will be disabled and will never be serviced The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 4 instructions Thi...

Page 244: ...s 1 requests or PEC requests are still serviced in this case In this way the interrupt sources excluding PEC requests are assigned to 3 classes of priority rather than to 7 different levels as the hardware support would do Table 5 9 Software Controlled Interrupt Classes Example ILVL Priority Group Level Interpretation 7 6 5 4 3 2 1 0 15 PEC service on up to 8 channels 14 13 12 X X X X X X X X Inte...

Page 245: ...viced so the CPU now executes on the new level The register bank select field BANK in PSW is changed to select the register bank associated with the interrupt request The association between interrupt requests and register banks are partly pre defined and can partly be programmed The interrupt request flag of the source being serviced is cleared IP and CSP are loaded with the vector associated wit...

Page 246: ... CP is simply POPped from the system stack which returns the registers to the original global bank Resources used by the interrupting program such as the DPPs must eventually be saved and restored Note There are certain timing restrictions during context switching that are associated with pipeline behavior Switching Context by changing the selected register bank automatically updates bitfield BANK...

Page 247: ...RSEL1 GPRSEL0 rw rw rw rw rw rw rw rw Field Bits Type Description GPRSEL0 GPRSEL1 GPRSEL2 GPRSEL3 GPRSEL4 GPRSEL5 GPRSEL6 GPRSEL7 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 rw Register Bank Selection 00B Global register bank 01B Reserved 10B Local register bank 1 11B Local register bank 2 Table 5 10 Assignment of Register Bank Control Fields Bank Select Control Register Interrupt Node Priority Notes Re...

Page 248: ...by the node control register IC The specific request flags within ISNC registers must be reset by software contrary to the node request bits which are cleared automatically Table 5 11 Sub Node Control Bit Allocation Interrupt Node Interrupt Sources Control EOPIC PEC channels 7 0 PECISNC RTC_IC RTC overflow of T14 CNT0 CNT3 RTC_ISNC CC2_CC16IC CAPCOM2 request ERU request 0 ISSR CC2_CC17IC CAPCOM2 r...

Page 249: ...terrupt source and the interrupt vector of this source will be used to service the external interrupt request Note In order to use any of the listed pins as an external interrupt input it must be switched to input mode via its port control register When port pins CCxIO are to be used as external interrupt input pins bitfield CCMODx in the control register of the corresponding capture compare regis...

Page 250: ...imer registers T2 or T4 based on the transition at pins T2IN or T4IN When the interrupt enable bits T2IE or T4IE are set a PEC request or an interrupt request for vector T2INT or T4INT will be generated Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5CON...

Page 251: ...tration and receive highest priority The standard OCDS service requests are routed to the CPU Action Control Unit together with the arbitrated interrupt PEC requests The service request with the higher priority is sent to the CPU to be serviced If both the interrupt PEC request and the OCDS request have the same priority level the interrupt PEC request wins This approach ensures precise break cont...

Page 252: ...s the time from activating a request signal at the interrupt controller ITC until the corresponding instruction reaches the pipeline s execution stage Table 5 13 lists the consecutive steps required for this process Table 5 13 Steps Contributing to Service Request Latency Description of Step Interrupt Response PEC Response Request arbitration in 3 stages leads to acceptance by the CPU see Section ...

Page 253: ...UCON1 Context switching is executed before the intended action takes place see Section 5 6 Time critical instructions can be programmed non destructive and can be executed before switching context for the remaining part of the interrupt service routine Table 5 14 Additional Delays Caused by System Logic Reason for Delay Interrupt Response PEC Response Interrupt controller busy because the previous...

Page 254: ...ce routine is loaded from register VECSEG No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU priority level and the selected register bank in register PSW are not modified by the TRAP instruction so the service routine is ...

Page 255: ...ch caused the exception Each trap function is indicated by a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 The reset functions may be regarded as a type of trap Reset functions have the highest system priority trap priority III Class A traps have the second highest priority trap priority II on the 3rd rank are Class B traps so a Class ...

Page 256: ...ow the contents of register STKOV STKUF 13 rwh Stack Underflow Flag 0B No stack underflow event detected 1B The current stack pointer value exceeds the contents of register STKUN SOFTBRK 12 rwh Software Break 0B No software break event detected 1B Software break event detected SR1 11 rwh System Request 1 Flag 0B No trigger detected 1B The selected condition has been detected UNDOPC 7 rwh Undefined...

Page 257: ...ruction or sequence the pipeline is canceled and the IP of the instruction following the last one executed is pushed on the stack Therefore in the case of a Class A trap the stack always contains the IP of the first not executed instruction in the instruction flow Note The Branch Folding Unit allows the execution of a branch instruction in parallel with the preceding instruction The pre processed ...

Page 258: ...ntains the IP of the first following not executed instruction in the instruction flow Note The Branch Folding Unit allows the execution of a branch instruction in parallel with the preceding instruction The pre processed branch instruction is combined with the preceding instruction The branch is executed together with the instruction causing the Class B trap The IP of the first following not execu...

Page 259: ... instruction currently being executed by the CPU is a SBRK instruction the SOFTBRK flag is set in register TFR and the CPU enters the software break debug routine The flag generation of the software break instruction can be disabled by the On chip Emulation Module In this case the instruction only breaks the instruction flow and signals this event to the debugger the flag is not set and the trap w...

Page 260: ...an access error additionally the soft trap code 1E9BH is issued Protection Fault Trap B Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction and the byte following the opcode is not the complement of the opcode the PRTFLT flag in register TFR is set and the CPU enters the protection fault tra...

Page 261: ...ap Generation see Chapter 6 12 Memory Content Protection see Chapter 6 13 Register Access Control see Chapter 6 14 Miscellaneous System Registers see Chapter 6 15 SCU Registers and Address map see Chapter 6 16 Important Information Register Programming The System Control Unit contains special function registers which can not be programmed in an arbitrary order in particular due to the usage of an ...

Page 262: ...speed system clock or can create a high speed system clock without external input The CGU consists of a Clock Generator and a Clock Control Unit CCU Figure 6 1 Clock Generation Unit Block Diagram The input connections of the CGU are described in Chapter 6 17 1 The following clock signals are generated System clock fSYS RTC count clock fRTC Wake Up Timer WUT clock fWUT External clock fEXT Chapter 6...

Page 263: ... PLLCON 3 SYSCON 0 WUOSCCON HPOSCCON PLLOSCCON PLLSTAT PLLCON0 PLLCON1 PLLCON2 PLLCON3 SYSCON0 STATCLR 0 STATCLR1 RTCCLKCON EXTCON STATCLR 0 STATCLR 1 RTCCLKCON PLL Configuration 2 Register PLL Configuration 3 Register System Control 0 Register Status Clear 0 Register PLL Status Clear 1 Register RTC Clock Control Register EXTCON External Clock Control Register WUOSCCON HPOSCCON PLLOSCCON PLLSTAT P...

Page 264: ...th XTAL1 as input and XTAL2 as output Figure 6 4 and Figure 6 3 show the recommended external circuitries for both operating modes External Crystal Mode and External Input Clock Mode 6 1 3 1 External Input Clock Mode An external clock signal is supplied directly not using an external crystal and bypassing the amplifier of the oscillator The maximum allowed input frequency depends on the characteri...

Page 265: ...to a high speed system clock for maximum performance The PLL also has fail safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock It can execute emergency actions if it loses its lock on the external clock This module is a phase locked loop for integer frequency synthesis It allows the use of input and output frequenci...

Page 266: ...the two clocks and accordingly controls the frequency of the VCO fVCO A PLL lock detection unit monitors and signals this condition The phase detection logic continues to monitor the two clocks and adjusts the VCO clock if required The PLL output clock fPLL is derived from the VCO clock using the K2 Divider or from the oscillator clockusing the K1 Divider The following figure shows the PLL block s...

Page 267: ...output frequency of the Voltage Controlled Oscillator VCO fVCObase is divided by a factor K2 The output frequency is given by 6 3 PLL Power Saving Modes PLL Power Down Mode The PLL offers a Power Down Mode to save power if the PLL is not needed at all While the PLL is in Power Down Mode no PLL output frequency is generated PLL Sleep Mode The PLL offers a Sleep Mode also called VCO Power Down Mode ...

Page 268: ...cally entered on a PLL VCO Loss of Lock event if bit PLLCON1 EMFINDISEN is cleared This mechanism allows a fail safe operation of the PLL as in emergency cases still a clock is available The frequency of the Unlocked Mode fVCObase is listed in the Data Sheet Note Changing the system operation frequency by changing the value of the K2 Divider or the VCO range has a direct influence on the power con...

Page 269: ...ation of the two dividers P and N has a direct influence on the VCO frequency and leads to a loss of the VCO Lock status A modification of the K2 divider has no impact on the VCO Lock status but changes the PLL output frequency Note Changing the system operation frequency by changing the value of the K2 Divider has a direct influence on the power consumption of the device Therefore this has to be ...

Page 270: ...de is entered when the status bit PLLSTAT VCOBYST is set Now the Normal Mode is entered The trap status flag for the VCO Lock trap should be cleared and then enabled again The intended PLL output target frequency can be configured by changing only the K2 Divider Depending on the selected divider value of the K2 Divider the duty cycle of the clock is selected This can have an impact on the operatio...

Page 271: ...de Diagram The Prescaler Mode is selected by the following setting PLLCON0 VCOBY 1 The Prescaler Mode is entered when all following conditions are true PLLSTAT VCOBYST 0 HPOSCCON PLLV 1 Operation in Prescaler Mode requires an input clock frequency fR If fIN is selected as clock source for fR it is recommended to check and monitor if an input frequency fOSC is available at all by checking HPOSCCON ...

Page 272: ...the status bit PLLSTAT VCOBYST is set Configuration and Operation of the PLL Power Down Mode The Power Down Mode is entered by setting bit PLLCON0 PLLPWD While the PLL is in Power Down Mode no PLL output frequency is generated Configuration and Operation of the PLL Sleep Mode The Sleep Mode also called VCO Power Down Mode is entered by setting bit PLLCON0 VCOPWD While the PLL is in Sleep Mode only...

Page 273: ...ystem Control Unit SCU User s Manual 6 13 V2 1 2008 08 SCU V1 13 Note The oscillator watchdog requires the trimmed currenct controlled clock fINT as a reference Therefore it can only be used HPOSCCON PLLV is valid while the clock source is active ...

Page 274: ...ed After switching to Prescaler Mode NDIV and PDIV can be adjusted Before deselecting the Prescaler Mode the RESLD bit has to be set and then the VCOLOCK flag has to be checked Only when the VCOLOCK flag is set again the Prescaler Mode may be deselected Before changing VCOSEL the Prescaler Mode must be selected Note PDIV and NDIV can also be switched in Normal Mode When changing NDIV it must be re...

Page 275: ...k OSC_HP fOSC Wake up clock fWU Input CLKIN1 as Direct Clock Input fCLKIN1 Input CLKIN2 as Direct Clock Input fCLKIN2 6 1 5 1 Clock Generation Different clock sources can be selected for the generated clock signals Note The selected clock sources are affected by the start up procedure See chapter Device Status after Start up for the register values set by the different start up procedures System C...

Page 276: ...it System Clock Generation CCU_SYSCLK _EXT vsd fWU fOSC fPLL M U X 00 01 10 11 M U X 00 01 10 11 M U X 0 1 System Clock Selection fSYS SYSCON0 CLKSEL SYSCON0 EMCLKSEL SYSCON 0 EMCLKSELEN PLLCON1 EMCLKEN HPOSCCON EMCLKEN OSCWDT Emergency Event VCOLCK Emergency Event to EXTCLK selection Emergency Clock fCLKIN1 Master Clock Multiplexer MCM ...

Page 277: ...nous mode in the module itself The asynchronous clock for the RTC can be selected out of following clock sources in the CCU PLL clock fPLL The oscillator clock OSC_HP fOSC Input CLKIN2 as Direct Clock Input fCLKIN2 Wake up clock fWU Figure 6 10 Clock Control Unit RTC Clock Generation CCU_RTCCLK_EXT vsd fWU fOSC fPLL M U X 00 01 10 11 M U X 0 1 to RTC block RTCCLKCON RTCCLKSEL fCLKIN2 fSYS RTCCLKCO...

Page 278: ...he input clock fIN is no more active Both events can be detected and are indicated to the application software The clock system takes appropriate actions where necessary so the device and the application is never left without an alternate clock signal Oscillator Watchdog Event If the clock frequency of the external source drops below a limit value the oscillator watchdog OSCWDT see Chapter 6 1 4 5...

Page 279: ...NDIS 1 and the PLL clock slows down to its VCO base frequency System Behavior Emergency routines can be executed with the alternate clock emergency clock or VCO base frequency The application can then enter a safe status and stop operation or it can switch to an emergency operating mode where a reduced performance and or feature set is provided The Programmer s Guide describes both how to enable t...

Page 280: ...anging bit field EXTCON SEL can lead to spikes at pin EXTCLK Figure 6 11 EXTCLK Generation 6 1 6 1 Programmable Frequency Output The programmable frequency output fOUT can be selected as clock output EXTCLK This clock can be controlled via software and so can be adapted to the requirements of the connected external circuitry The programmability also extends the power management to a system level a...

Page 281: ...fOUT is started EXTCON FOEN is set counter FOCNT is loaded from EXTCON FORV When OUT is stopped EXTCON FOEN is cleared counter FOCNT is stopped when fOUT has reached or is 0 Register EXTCON provides control over the output generation frequency waveform activation as well as all status information EXTCON FOTL CCU_EXTCLK_Counter vsd 0 EXTCON FOTL fOUT Counter fSYS FOTL M U X Ctrl EXTCON FOEN Reload ...

Page 282: ...n of one fSYS cycle for all reload values EXTCON FORV 0 For EXTCON FORV 0 the output frequency corresponds to fSYS When a reference clock is required e g for the bus interface fSYS must be selected directly mc_xc16x_foutwaves vsd fSYS fOU T FORV 0 1 2 1 2 fOU T FORV 2 1 2 fOU T FORV 5 FOEN 1 1 FOSS 1 Output of Counter 2 FOSS 0 Output of Toggle Latch FOEN 0 The counter starts here The counter stops...

Page 283: ...rw rw rw Field Bits Type Description FREQSEL 1 0 rw Frequency Selection 00B fWU is approximately 500 kHz 01B fWU is approximately 300 kHz 10B fWU is approximately 200 kHz 11B fWU is approximately 130 kHz Note This value must not be changed while fWU is used as clock source for any logic 0 3 2 rw Reserved Must be written with reset value 00B DIS 4 rw Clock Disable 0B The oscillator is switched on a...

Page 284: ...pe Description PLLV 0 rh Oscillator for PLL Valid Status Bit This bit indicates whether the frequency output of OSC_HP is usable This is checked by the Oscillator Watchdog of the PLL 0B The OSC_HP frequency is not usable The frequency is below the limit 1B The OSC_HP frequency is usable The frequency is not below the limit For more information see Chapter 6 1 4 5 OSCWDTRST 1 w Oscillator Watchdog ...

Page 285: ...Y 8 rw Shaper Bypass The shaper forms a proper signal from the input signal This bit must be 0 for proper operation 0B The shaper is not bypassed 1B The shaper is bypassed EMCLKEN 9 rw OSCWDT Emergency System Clock Source Select Enable This bit requests the master clock multiplexer MCM to switch to an alternate clock selected by bit field SYSCON0 EMCLKSEL in an OSCWDT emergency case 0B MCM remains...

Page 286: ...en cleared by writing 1 to bit STATCLR1 OSC2L1CLR 0B No change of PLLV detected 1B Bit PLLV has been cleared at least once OSC2L0 12 rh OSC_HP Usable Frequency Event This sticky bit indicates if bit PLLV has been set since OSC2L0 has last been cleared by writing 1 to bit STATCLR1 OSC2L0CLR 0B No change of PLLV detected 1B PLLV has been set at least once 0 15 13 r Reserved Read as 0 should be writt...

Page 287: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OSCTRIM OSC PD r rw rw Field Bits Type Description OSCPD 0 rw Clock Source Power Saving Mode 0B Trimmed current controlled clock source is active 1B Trimmed current controlled clock source is off OSCTRIM 9 1 rw Clock Source Trim Configuration This value is used to adjust the frequency range of the current controlled clock source Do not change this value when w...

Page 288: ... Mode 1B The PLL clock is derived from divider K2 Normal Unlocked Mode Note Coding of PLLCON0 VCOBY and VCOBYST are different PWDSTAT 1 rh PLL Power saving Mode Status 0B The PLL is operable 1B The digital part of the PLL is disabled OSCSELST 2 rh Oscillator Input Selection Status 0B External input clock source for the PLL fIN 1B Internal input clock source for the PLL VCOLOCK 3 rh PLL VCO Lock St...

Page 289: ...The K1 Divider operates with the value defined in bit field PLLCON2 K1DIV K2RDY 8 rh K2 Divider Ready Status 0B Bit field PLLCON3 K2DIV has been changed new K2 divider value not yet used 1B The K2 Divider operates with the value defined in bit field PLLCON3 K2DIV FINDIS 9 rh Input Clock Disconnect Select Status 0B The VCO is connected to the reference clock 1B The VCO is disconnected from the refe...

Page 290: ...eared by writing 1 to bit STATCLR1 VCOL1CLR 0B No rising edge detected 1B VCO lock was reached REGSTAT 12 rh PLL Power Regulator Status The PLL is powered by a separate internal regulator 0B The PLL is not powered off 1B The PLL is powered operation possible Note Software can control this bit by writing 1 to bits REGENSET or REGENCLR in register PLLCON0 0 4 15 13 r Reserved Read as 0 should be wri...

Page 291: ...n 1B Bit PLLSTAT VCOL0 is cleared VCOL1CLR 1 w VCOL1 Clear Trigger 0B No action 1B Bit PLLSTAT VCOL1 is cleared OSC2L1CLR 2 w OSC2L1 Clear Trigger 0B No action 1B Bits HPOSCCON OSC2L1 is cleared OSC2L0CLR 3 w OSC2L0 Clear Trigger 0B No action 1B Bit HPOSCCON OSC2L0 is cleared SETFINDIS 4 w Set Status Bit PLLSTAT FINDIS 0B No action 1B Bit PLLSTAT FINDIS is set The VCO input clock is disconnected C...

Page 292: ... bypassed Bit PLLSTAT VCOBYST shows the actually selected divider Note Coding of VCOBY and PLLSTAT VCOBYST are different VCOPWD 1 rw VCO Power Saving Mode 0B Normal behavior 1B The VCO is put into a power saving mode and can no longer be used Only the Prescaler Mode is active if previously selected VCOSEL 3 2 rw VCO Range Select The values for the different settings are listed in the data sheet RE...

Page 293: ...tes is NDIV 1 Only values between N 8 and N 28 are allowed for VCOSEL 00B Only values between N 16 and N 40 are allowed for VCOSEL 01B Outside of this range no stable operation is guaranteed NACK 15 rw N Divider Ready Acknowledge Setting this bit provides the acknowledge signal to NRDY 0 6 7 14 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 294: ...external clock as input for PLL 1B Select trimmed current controlled clock as input for PLL RESLD 2 w Restart VCO Lock Detection Setting this bit will reset bit PLLSTAT VCOLOCK and restart the VCO lock detection AOSCSEL 3 rw Asynchronous Oscillator Input Selection This bit overrules the setting of bit OSCSEL 0B Configuration is controlled via bit OSCSEL 1B Select asynchronously trimmed current con...

Page 295: ...VCOLCK emergency case 0B No action 1B PLLSTAT FINDIS is set in a VCOLCK emergency case Note Please refer to the Programmer s Guide for a description of the proper handling PDIV 11 8 rw P Divider Value The value the P Divider operates is PDIV 1 PACK 15 rw P Divider Ready Acknowledge Setting this bit provides the acknowledge to PRDY 0 4 7 14 12 r Reserved Read as 0 should be written with 0 Field Bit...

Page 296: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 K1 ACK 0 K1DIV rw r rw Field Bits Type Description K1DIV 9 0 rw K1 Divider Value The value the K1 Divider operates is K1DIV 1 K1ACK 15 rw K1 Divider Ready Acknowledge1 Setting this bit provides the acknowledge to K1RDY 1 Please refer to the Programmer s Guide for a description of the proper handling 0 14 10 r Reserved Read as 0 should be written with 0 ...

Page 297: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 K2 ACK 0 K2DIV rw r rw Field Bits Type Description K2DIV 9 0 rw K2 Divider Value The value the K2 Divider operates is K2DIV 1 K2ACK 15 rw K2 Divider Ready Acknowledge1 Setting this bit provides the acknowledge to K2RDY 1 Please refer to the Programmer s Guide for a description of the proper handling 0 14 10 r Reserved Read as 0 should be written with 0 ...

Page 298: ...C is used 10B The PLL clock fPLL is used 11B CLKIN1 as direct input clock fCLKIN1 is used EMCLKSEL 4 3 rw Emergency Clock Select This bit field defines the clock source that is used as system clock in case of an OSCWDT or VCOLCK emergency event 00B The Wake up clock fWU is used 01B The oscillator clock OSC_HP fOSC is used 10B The PLL clock fPLL is used 11B CLKIN1 as direct input clock fCLKIN1 is u...

Page 299: ...t occurred since EMSVCO has been cleared last 1B A VCOLCK emergency event has occurred Note This bit is only set if EMCLKSELEN is set SELSTAT 15 rh Clock Select Status 0B The standard configuration from bit field CLKSEL is used currently 1B The configuration from bit field EMCLKSEL is used currently 0 2 5 11 7 14 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 300: ...ESFR F0E0H 70H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 EMC VCO EMC OSC 0 r w w r Field Bits Type Description EMCOSC 12 w EMSOSC Clear Trigger 0B No action 1B Bit SYSCON0 EMSOSC is cleared EMCVCO 13 w EMSVCO Clear Trigger 0B No action 1B Bit SYSCON0 EMSVCO is cleared 0 11 0 15 14 r Reserved Read as 0 should be written with 0 ...

Page 301: ...s Type Description RTCCLKSEL 1 0 rw RTC Clock Select This bit field defines the count clock source for the RTC 00B The PLL clock fPLL is used 01B The oscillator clock OSC_HP fOSC is used 10B The Wake up clock signal fWU is used 11B CLKIN2 as direct input clock fCLKIN2 is used RTCCM 2 rw RTC Clocking Mode 0B Asynchronous Mode The RTC internally operates with fRTC No register access is possible 1B S...

Page 302: ...zero 1B The configured external clock signal is provided as alternate output signal SEL 4 1 rw External Clock Select Selects the clock signal to be routed to the EXTCLK pin 0000BSystem clock fSYS 0001BProgrammable clock signal fOUT 0010BPLL output clock fPLL 0011BOscillator clock fOSC 0100BWake up clock fWU 0101BDirect Input clock fCLKIN1 1000BRTC count clock fRTC All other combination are reserve...

Page 303: ...l 6 43 V2 1 2008 08 SCU V1 13 FOEN 15 rw Frequency Output Enable 0B Frequency output generation stops when fOUT is becomes low 1B FOCNT is running fOUT is gated to pin First reload after 0 1 transition 0 5 7 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 304: ...usually derived from the trimmed current controlled wake up clock fWU Figure 6 14 Wake up Timer Logic 6 2 1 Wake up Timer Operation The Wake up Timer start and stop is controlled by the Run Control logic The timer can be started in the following ways bit WUCR AON is set AND the Power State Controller PSC see Chapter 6 5 5 generates a start trigger bit WUCR RUN is set When the timer is started the ...

Page 305: ... of Wake up Period The actual frequency of the trimmed current controlled wake up clock OSC_WU can be measured prior to entering power save mode in order to adjust the number of clock cycles to be counted value written to WIC and such to define the time until wake up The period of OSC_WU can be measured by evaluating its synchronized clock output which can generate an interrupt request or which ca...

Page 306: ...R Via this register the status and configuration of the WIC counter is done WICR Wake up Interval Count Register ESFR F0B0H 58H Reset Value FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WIC rwh Field Bits Type Description WIC 15 0 rwh Wake up Interval Counter This free running 16 bit counter counts down and issues a trigger when its count reaches zero ...

Page 307: ... 0 w Control Field for RUN 00B No action 01B Set bit RUN 10B Clear bit RUN 11B Reserved do not use this combination AONCON 3 2 w Control Field for AON 00B No action 01B Set bit AON 10B Clear bit AON 11B Reserved do not use this combination ASPCON 5 4 w Control Field for ASP 00B No action 01B Set bit ASP 10B Clear bit ASP 11B Reserved do not use this combination CLRTRG 7 w Clear Bit WUTRG 0B No act...

Page 308: ...B Wake up counter is started by software only 1B Wake up counter can be started by the PSC mechanism ASP 10 rh Auto Stop Indicator 0B Wake up counter runs continuously 1B Wake up counter stops after generating a trigger when reaching zero TTSTAT 14 rh Trim Trigger Status 0B No trim trigger event is active No trim interrupt trigger is generated 1B A trim trigger event is active A trim interrupt tri...

Page 309: ...r the complete system are supported 6 3 1 1 Device Reset Hierarchy The device reset hierarchy is divided according to the power domains see Chapter 6 5 into following linked levels Level 1 I O domain power domain DMP_B Level 2 Wake up domain power domain DMP_M Level 3 System domain power domain DMP_1 If a power domain level is deactivated all resets of the deactivated level and all resets of all l...

Page 310: ...ts it had before the last reset To identify the type and the trigger of the latest reset registers RSTSTATx and SWDCON1 may be evaluated according to the following table The latest reset that has occured is always the reset of the highest type If two reset triggers of the same type are indicated this means that the two triggers have been active at the same time If two or more reset triggers of a d...

Page 311: ... for all application relevant resets Internal Application Reset and Application Reset RSTCNTD is the reset counter that controls the reset length for the debug reset The reset counters control the length of the internal resets This can be used to configure the duration of a reset output via the ESRx pins so this matches with the reset input requirements of external blocks connected to these signal...

Page 312: ...gher is currently asserted Example1 Reset request trigger A is asserted and leads to an Application Reset If the reset request trigger is de asserted before RSTCNTA reached zero the Application Reset is de asserted when RSTCNTA reaches zero If the reset request trigger is de asserted after RSTCNTA reached zero the Application Reset is de asserted when the reset request trigger is de asserted Table...

Page 313: ... zero If the reset request trigger B is de asserted after RSTCNTA reached zero the Application Reset is de asserted when the reset request trigger B is de asserted 6 3 3 Debug Reset Assertion Unlike the other reset types a Debug Reset can only be asserted if the following two conditions are valid A reset request trigger is asserted that request a debug reset An Application Reset is already active ...

Page 314: ...N0 L1RSTEN 1B If the bit PVCMCON0 L1RSTEN 1B a request trigger is asserted for PVC_M1 upon a level check match If the bit PVCMCON0 L2RSTEN 1B a request trigger is asserted for PVC_M2 upon a level check match If the core power supply is below the value required for proper functionality of the application power domain PVC_1 a reset request trigger can be forwarded to the system The generation of a P...

Page 315: ...st trigger leads to a configurable reset The type of reset can be configured via RSTCON1 WDT A WDT reset is requested on a WDT overflow event For more information see Chapter 6 11 CPU A CPU reset request trigger leads to a configurable reset The type of reset can be configured via RSTCON0 CPU A CPU reset is requested when instruction SRST is executed Memory Parity A MP reset request trigger leads ...

Page 316: ...ated PVC_M1 Activated Activated Activated PVC_M2 Activated Activated Activated PVC_11 Activated Activated Activated PVC_12 Activated Activated Activated ESR0 Configurable Configurable Not Activated ESR1 Configurable Configurable Not Activated ESR2 Configurable Configurable Not Activated WDT Configurable Configurable Not Activated SW Configurable Configurable Not Activated CPU Configurable Configur...

Page 317: ... is not affected by the reset DPRAM Not affected reliable Not affected reliable Not affected reliable PSRAM Not affected reliable Not affected reliable Not affected reliable DSRAM Not affected reliable Not affected reliable Not affected reliable Flash Memory X 2 2 Parts of the flash memory block are only reset by a Power on Reset For more detail see the flash chapter X 2 Not affected reliable JTAG...

Page 318: ...Field Bits Type Description CPU 13 12 rh CPU Reset Type Status 00B The CPU reset trigger was not relevant for the last reset 01B Reserved 10B The CPU reset trigger was relevant for the last reset Internal Application and Application Resets were generated 11B The CPU reset trigger was relevant for the last reset Application Reset was generated SW 15 14 rh Software Reset Type Status 00B The Software...

Page 319: ... 11B The ESR0 reset trigger was relevant for the last reset Application Reset was generated ESR1 3 2 rh ESR1 Reset Status 00B The ESR1 reset trigger was not relevant for the last reset 01B Reserved 10B The ESR1 reset trigger was relevant for the last reset Internal Application and Application Resets were generated 11B The ESR1 reset trigger was relevant for the last reset Application Reset was gen...

Page 320: ...r the last reset Application Reset was generated STM 13 12 rh Power on for DMP_M Reset Status 00B The power on reset for DMP_M reset trigger was not relevant for the last reset 01B The power on reset for DMP_M reset trigger was not relevant for the last reset 10B The power on reset for DMP_M reset trigger was not relevant for the last reset 11B The power on reset for DMP_M reset trigger was releva...

Page 321: ... trigger was relevant for the last reset OJCONF1 5 4 rh OJCONF1 Reset Status 00B The OJCONF1 reset trigger was not relevant for the last reset 01B The OJCONF1 reset trigger was not relevant for the last reset 10B The OJCONF1 reset trigger was not relevant for the last reset 11B The OJCONF1 reset trigger was relevant for the last reset Debug Reset was generated OJCONF2 7 6 rh OJCONF2 Reset Status 0...

Page 322: ... reset trigger was not relevant for the last reset 01B The OJCONF3 reset trigger was not relevant for the last reset 10B The OJCONF3 reset trigger was not relevant for the last reset 11B The OJCONF3 reset trigger was relevant for the last reset Application Reset was generated 0 3 2 15 10 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 323: ...pe Selection This bit field defines which reset types are generated by a CPU reset request trigger 00B No reset is generated 01B Reserved do not use this combination 10B Internal Application and Application Resets are generated 11B Application Reset is generated SW 15 14 rw Software Reset Type Selection This bit field defines which reset types are generated by a software reset request trigger 00B ...

Page 324: ...ion 10B Internal Application and Application Resets are generated 11B Application Reset is generated ESR1 3 2 rw ESR1 Reset Type Selection This bit field defines which reset types are generated by a ESR1 reset request trigger 00B No reset is generated 01B Reserved do not use this combination 10B Internal Application and Application Resets are generated 11B Application Reset is generated ESR2 5 4 r...

Page 325: ...ot use this combination 10B Internal Application and Application Resets are generated 11B Application Reset is generated MP 9 8 rw MP Reset Type Selection This bit field defines which reset types are generated by a MP reset request trigger 00B No reset is generated 01B Reserved do not use this combination 10B Internal Application and Application Resets are generated 11B Application Reset is genera...

Page 326: ...defines the reload value of RSTCNTA This value is always used when counter RSTCNTA is started This counter value is used for Internal Application and Application Resets In case of an ESRx reset the counter value must be not less than the reset value RELD 15 8 rw Debug Reset Counter Reload Value This bit field defines the reload value of RSTCNTD This value is always used when counter RSTCNTD is sta...

Page 327: ...election 0B Bit field STSTAT HWCFG is not updated with the content of SWCFG upon an Application Reset 1B Bit field STSTAT HWCFG is updated with the content of SWCFG upon an Application Reset SWRSTREQ 1 w Software Reset Request 0B No software reset is requested 1B A software reset request trigger is generated SWCFG 15 8 rw Software Boot Configuration A valid software boot configuration also differe...

Page 328: ...wer domain DMP_M see Section 6 5 and ESRCFGx SEDCON if a clock is active in the power domain DMP_M Additionally there is a digital 3 stage median filter DF to suppress spikes The signal at ESRx pin has to be held at the active signal level for at least 2 system clock cycles fSYS in order to generate a trigger If the power domain DMP_M is not clocked then the filter is not taken into account The di...

Page 329: ... more than one pin shall be used for ESR trigger generation then any signal at the respective pin must have an inactive high level Pin ESR0 does not offer an overlay with other product functions For information which other peripheral input signal is on an ESR overlay pin see Chapter 6 17 2 The following figure shows the the ESR Input selection function for ESR1 and ESR2 ESR _control vsd Reset Cont...

Page 330: ...lability of pins ESR1 and ESR2 is device and package dependent and is described in the data sheet Even if pin ESR1 or ESR2 are not available in the device an overlay with other product functions i e inputs of serial interfaces can be configured via register ESREXCON1 ESREXCON2 to trigger ESR operations ESRx ESRx_selection_MR vsd Input 0 Input 1 Input 2 Input 3 Input 5 Input 4 ESREXCONx ESRx Contro...

Page 331: ...eset only while RSTCNTA is active It deactivates the output stage when the time defined by RSTCNTCON RELA has passed For more information about the reset system see Chapter 6 3 6 4 1 3 ESR as Trap Trigger The ESR can request traps The control mechanism if and which trap is requested is located in the trap control logic For more information see Chapter 6 12 6 4 1 4 ESR as Wake up Trigger for the PS...

Page 332: ...lock off Mode on an external Interrupt or CCU6x trigger and on a CAN or USIC operation Request to enter a Clock off Mode on an external Interrupt or CCU6x trigger and on a CAN or USIC operation Stop input for the CCU6x modules on an external event For more information about the external interrupt trigger see Chapter 6 8 Table 6 6 Additional ESR0 Functions Function Module Function is Implemented Tr...

Page 333: ... V2 1 2008 08 SCU V1 13 Table 6 8 Additional ESR2 Functions Function Module Function is Implemented Trap Generation Trap Generation PSC Wake up Request OSC_WU enable Power State Machine PSC and CGU Peripheral Normal Mode Request Global Mode Control GSC Fast External Stop of CCU6x CCU6x ...

Page 334: ...ion I O Output Characteristics 0000B No pull device activated Input is not inverted the input stage is active in power down mode 0001B Pull down device activated 0010B Pull up device activated 0011B No pull device activated 0100B No pull device activated Input is inverted the input stage is active in power down mode 0101B Pull down device activated 0110B Pull up device activated 0111B No pull devi...

Page 335: ...nable This bit enables disables the ESR1 pin for the activation of all ESR1 related actions 0B The input from pin ESR1 is disabled 1B The input from pin ESR1 is enabled P24EN 1 rw Port 2 4 Pin Enable This bit enables disables the Port 2 4 pin for the activation of all ESR1 related actions 0B The input from port pin P2 4 is disabled 1B The input from port pin P2 4 is enabled P30EN 2 rw Port 3 0 Pin...

Page 336: ...is enabled P12EN 5 rw Port 1 2 Pin Enable This bit enables disables the Port 1 2 pin for the activation of all ESR1 related actions 0B The input from port pin P1 2 is disabled 1B The input from port pin P1 2 is enabled P21EN 6 rw Port 2 1 Pin Enable This bit enables disables the Port 2 1 pin for the activation of all ESR1 related actions 0B The input from port pin P2 1 is disabled 1B The input fro...

Page 337: ... Port 2 3 pin for the activation of all ESR2 related actions 0B The input from port pin P2 3 is disabled 1B The input from port pin P2 3 is enabled P70EN 2 rw Port 7 0 Pin Enable This bit enables disables the Port 7 0 pin for the activation of all ESR2 related actions 0B The input from port pin P7 0 is disabled 1B The input from port pin P7 0 is enabled P1014EN 3 rw Port 10 14 Pin Enable This bit ...

Page 338: ...of all ESR2 related actions 0B The input from port pin P1 3 is disabled 1B The input from port pin P1 3 is enabled P22EN 6 rw Port 2 2 Pin Enable This bit enables disables the Port 2 2 pin for the activation of all ESR2 related actions 0B The input from port pin P2 2 is disabled 1B The input from port pin P2 2 is enabled 0 15 7 rw Reserved Read as 0 should be written with 0 Field Bits Type Descrip...

Page 339: ... 4 3 2 1 0 0 AEDCON SEDCON IN OUT DF EN PC r rw rw rh rh rw rw Field Bits Type Description PC 3 0 rw Pin Control of ESRx This bit field controls the behavior of the associated ESRx pin The coding is described in Table 6 9 DFEN 4 rw Digital Filter Enable This bit defines if the 3 stage median filter of the ESRx is used or bypassed 0B The filter is bypassed 1B The filter is used OUT 5 rh Data Output...

Page 340: ...a raising AND falling edge Other combinations than 00B are only allowed if bit field AEDCON is configured to 00B AEDCON 10 9 rw Asynchronous Edge Detection Control This bit field defines the edges that lead to an ESRx trigger of the asynchronous path 00B No trigger is generated 01B A trigger is generated upon a raising edge 10B A trigger is generated upon a falling edge 11B A trigger is generated ...

Page 341: ... Bit ESRCFG0 OUT is unchanged 01B Bit ESRCFG0 OUT is set 10B Bit ESRCFG0 OUT is cleared 11B Reserved do not use this combination MOUT1 3 2 w Modification of ESRCFG1 OUT Writing to this bit field can modify the content of bit ESRCFG1 OUT for ESR1 It always reads 0 00B Bit ESRCFG1 OUT is unchanged 01B Bit ESRCFG1 OUT is set 10B Bit ESRCFG1 OUT is cleared 11B Reserved do not use this combination MOUT...

Page 342: ... DMP_A contains all ADC related I Os and DMP_B the remaining system and communication I Os The major part of the on chip logic is located in an independent core power domain DMP_1 A second smaller power domain DMP_M marked grey in the figure below controls wake up mechanism and other important device infrastructure plus a Standby RAM SBRAM The DMP_M and or DMP_1 can be either switched off i e disc...

Page 343: ...at provides two monitoring levels Each monitoring level can request an interrupt e g power fail warning or a reset depending on the voltage level A PVC is used to detect under voltage due to an external short see Chapter 6 5 2 By controlling the regulator a core power domain can be switched off to save the leakage current within this area see Chapter 6 5 3 Table 6 10 XC2200 Power Domains Supply an...

Page 344: ...amp down of the external supply voltage so the device can be brought into a save state without requiring an external power on reset PORST Monitoring the external power supply allows the usage of a low cost regulator without additional status signals standard 3 pin device Guarantee that the supply voltage for the EVRs is sufficient to generate a valid core voltage under every operating condition Fe...

Page 345: ...te The physical value for VVAL can found in the XC2200 data sheet The SWD provides two adjustable threshold levels LEV1 and LEV2 that can be individually programmed via SWDCON0 LEV1V and SWDCON0 LEV2V and deliver a compare value each The two compare results can be monitored via bits SWDCON0 L1OK and SWDCON0 L2OK A reset or interrupt request can be generated while the voltage level is below or equa...

Page 346: ...tage level and can be configured to monitor other voltage levels Note If the PORST pin is used it has the same functionality as the SWD Power Saving Mode of the SWD The two configurable thresholds can be disabled if not needed This is called the SWD Power Saving Mode The minimum operating voltage detection POR Brown out detection can not be disabled and it is always active The SWD Power Saving Mod...

Page 347: ... Level Threshold 1 Check Result 0B The supply voltage is below the Level Threshold 1 voltage LEV1V 1B The supply voltage is equal or above the Level Threshold 1 voltage LEV1V L1ACON 6 5 rw Level Threshold 1 Action Control This bit field defines which actions are requested if the supply voltage comparison matches the action level L1ALEV Following actions can be requested 00B No action is requested ...

Page 348: ...ge LEV2V L2ACON 14 13 rw Level Threshold 2 Action Control This bit field defines which actions are requested if the supply voltage comparison matches the action level L2ALEV Following actions can be requested 00B No action is requested 01B An interrupt is requested 10B A reset is requested 11B A reset and an interrupt are requested L2ALEV 15 rw Level Threshold 2 Action Level 0B When the supply vol...

Page 349: ...aving Mode Enable Clear 0B No action 1B Bit POWEN is cleared POWENSET 1 w SWD Power Saving Mode Enable Set 0B No action 1B Bit POWEN is set POWEN 2 rh SWD Power Saving Mode Enable 0B All SWD functions are enabled 1B The SWD Power Saving Mode is enabled Comparators are disabled PON 3 rh Power On Status Flag 0B No power on event occurred 1B A power on event occurred VDDP became greater than VVAL CLR...

Page 350: ...les the complete module Configurable action level A PVC provides two adjustable threshold levels LEV1 and LEV2 that can be individually programmed via PVCxCON0 LEV1V and PVCxCON0 LEV2V x M or 1 The current supply level of a domain is compared with the threshold values The two compare results can be monitored via bits PVCxCON0 LEV1OK and PVCxCON0 LEV2OK x M or 1 A reset or interrupt request can be ...

Page 351: ...rwh Level Threshold 1 Voltage This bit field defines the Level Threshold 1 that is compared with the DMP_1 core voltage The values for the different configurations are listed in the data sheet LEV1OK 3 rh Level Threshold 1 Check Result 0B The core supply voltage of the DMP_1 is below Level Threshold 1 voltage LEV1V 1B The core supply voltage of the DMP_1 is equal or above the Level Threshold 1 vol...

Page 352: ...mparison check was successful When a check is successful is defined via bit L1ALEV 0B No asynchronous actions are performed 1B Asynchronous actions can be performed LEV2V 10 8 rwh Level Threshold 2 Voltage This bit field defines the level of threshold 2 that is compared with the DMP_1 core voltage The values for the different configurations are listed in the data sheet LEV2OK 11 rh Level Threshold...

Page 353: ...sted L2RSTEN 14 rwh Level Threshold 2 Reset Request Enable This bit defines if a reset request trigger is requested if the comparison check was successful When a check is successful is defined via bit L2ALEV 0B No reset is requested 1B An reset is requested L2ASEN 15 rwh Level Threshold 2 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison check wa...

Page 354: ... Level Threshold 1 Check Result 0B The core supply voltage of the DMP_M is below Level Threshold 1 voltage LEV1V 1B The core supply voltage of the DMP_M is equal or above the Level Threshold 1 voltage LEV1V L1ALEV 4 rwh Level Threshold 1 Action Level 0B When the core supply voltage is below Level Threshold 1 voltage LEV1V the action configured by bits L1INTEN L1RSTEN and L1ASEN are requested 1B Wh...

Page 355: ...MP_M core supply voltage The values for the different configurations are listed in the data sheet LEV2OK 11 rh Level Threshold 2 Check Result 0B The core supply voltage of the DMP_M is below Level Threshold 2 voltage LEV2V 1B The core supply voltage of the DMP_M is equal or above the Level Threshold 2 voltage LEV2V L2ALEV 12 rwh Level Threshold 2 Action Level 0B When the core supply voltage is bel...

Page 356: ...heck was successful When a check is successful is defined via bit L2ALEV 0B No reset is requested 1B An reset is requested L2ASEN 15 rwh Level Threshold 2 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison check was successful When a check is successful is defined via bit L2ALEV 0B No asynchronous actions are performed 1B Asynchronous actions can ...

Page 357: ...d by an own Embedded Voltage Regulator EVR The core power domain DMP_M is controlled by the EVR_M The core power domain DMP_1 is controlled by the EVR_1 6 5 3 1 Power States Based on the various operating states of the EVRs several Power States are defined in order to achieve easily a power reduction Table 6 11 summarizes the power states used in the different Operating Modes Table 6 11 Power Stat...

Page 358: ... tolerates an external supply voltage provided through the pin VDDI that connects the external buffer capacitor The EVR configurations to select the desired voltage and reference pair are combined within EVR settings EVRxSETyyV x M or 1 and yy 10 or 15 Each setting contains a bit field VRSEL to select the voltage level and reference and a bit field to fine tune the voltage level VLEV One out of th...

Page 359: ...and the bit field EVRxSETyyV VRVAL are writable this should not be done the reset value of the setting registers is already defined in the way the different setting work As the core voltage depends on the LPR the LPR can be adjusted via bit field EVRxCON0 LPRLEV for application specific fine tuning High Precision Bandgap HP The HP bandgap of the system is used for following purposes Provide a very...

Page 360: ...is register 0 7 6 rw Reserved Must be written with reset value 00B RES1 8 rw Reserved Must be written with reset value 1B LPRDIS 9 rh Low Power Reference Disable 0B The LPR is enabled 1B The LPR is disabled This bit is updated by bit EVR1SETy LPRDIS CCLEV 11 10 rw Current Control Level The values for the different configurations are listed in the data sheet CCDIS 12 rh Current Control Disable 0B T...

Page 361: ...Description VLEV 5 0 rw Voltage Level Adjust This bit field adjusts the BG voltage and is trimmed by each device during production test to reach the default setting targets Do not change this value when writing to this register VRSEL 7 6 rw Voltage Reference Selection 00B 15VHP Full Voltage with high precision bandgap selected 01B 10V Reduced Voltage with low power reference selected 10B Reserved ...

Page 362: ...bled 1B The current control is disabled This bit updates bit EVR1CON0 CCDIS Note Before switching off the current control the CCLEV setting in EVR1CON0 has to be set to 00B EVRDIS 15 rw EVR_1 Disable 0B The EVR_1 is enabled 1B The EVR_1 is disabled This bit updates bit EVR1CON0 EVRDIS 0 8 11 10 14 13 rw Reserved Must be written with reset value 0 Field Bits Type Description ...

Page 363: ...iting to this register 0 7 6 rw Reserved Must be written with reset value 00B RES1 8 rw Reserved Must be written with 1 LPRDIS 9 rh Low Power Reference Disable 0B The LPR is enabled 1B The LPR is disabled This bit is updated by bit EVRMSETy LPRDIS CCLEV 11 10 rw Current Control Level The values for the different configurations are listed in the data sheet CCDIS 12 rh Current Control Disable 0B The...

Page 364: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 HP EN HPADJUST r rw rw Field Bits Type Description HPADJUST 7 0 rw HP Bandgap Adjustment This bit field is a device specific trimmvalue for the HP bandgap Do not change this value when writing to this register HPEN 8 rw HP Bandgap Enable 0B The HP bandgap is disabled 1B The HP bandgap is enabled 0 15 9 r Reserved Read as 0 should be written with 0 ...

Page 365: ...Description VLEV 5 0 rw Voltage Level Adjust This bit field adjusts the BG voltage and is trimmed by each device during production test to reach the default setting targets Do not change this value when writing to this register VRSEL 7 6 rw Voltage Reference Selection 00B 15VHP Full Voltage with high precision bandgap selected 01B 10V Reduced Voltage with low power reference selected 10B Reserved ...

Page 366: ...bled 1B The current control is disabled This bit updates bit EVRMCON0 CCDIS Note Before switching off the current control the CCLEV setting in EVRMCON0 has to be set to 00B EVRDIS 15 rw EVR_M Disable 0B The EVR_M is enabled 1B The EVR_M is disabled This bit updates bit EVR1CON0 EVRDIS 0 8 11 10 14 13 rw Reserved Must be written with reset value 0 Field Bits Type Description ...

Page 367: ... requires external buffer capacitances Please refer to the respective Data Sheet for the recommended values The current is delivered by the integrated pass devices Figure 6 19 Selecting the EVR for Core Supply Generating the core supply voltage with on chip resources provides full control of power reduction modes so the application can control and minimize the energy consumption of the XC2200 usin...

Page 368: ...nerating the core supply voltage externally requires additional efforts and circuitry to provide control over the power consumption of the XC2200 Note Running the XC2200 with external supplies requires a more complex power supply system but minimizes the heat dissipation on the chip MC_XC2X_POWER_EXT On chip EVR VDDPB VSS VDDI Ext Voltage Reg Microcontroller ...

Page 369: ...he ADC Adapting the core voltage level to the application needs lowering the core voltage level for a complete domain gives an additional power saving option that can and should be link with the previous options changes of the core voltage levels of the two core domains are controlled by the Power State Controller PSC the Power States define all legal combinations of the core voltage level for the...

Page 370: ...ill not trigger a power transfer The different triggers are separated into two different groups Ramp down triggers that request the transition into a power saving mode Only the software trigger can request a ramp down The software trigger can be generated by setting bit SEQCON SEQATRG Ramp up triggers that request the transition out of a power saving mode Synchronous ESR triggers can be used to re...

Page 371: ...d and modified when a voltage change is requested from the system Two sets of configuration data are needed to handle all power state transitions Sequence A is used for ramp down power transfers Sequence B is used for ramp up power transfers Sequence A it is invoked if a software trigger bit SEQBTRG in register SEQCON is set Sequence B it is invoked if at least one valid wake up trigger is asserte...

Page 372: ...ettings which are applied to the power system whilst a transition At the end of each power state transition the values from the last enabled step are copied to step 0 6 5 5 3 Power State Transition Controlling The PSC have to be pre configured before the transition sequence is started For a power state transition sequence using sequence B the control registers SEQBSTEPx Step x PSC _Sequence _1 SEQ...

Page 373: ...continuation the asynchronous event has to be selected If the system clock is not stopped synchronous continuation is selected If the system clock is stopped asynchronous continuation is selected This configuration is ignored if the step is configured to be skipped The system clock is enabled again as soon as the selected trigger condition bit field TRGSEL in the associated register is valid again...

Page 374: ...ver the required continuation event occurs the next step is executed This configuration is ignored if the step is configured to be skipped 6 5 5 4 Trigger Handling during a Power Transition A power transition is an atomic operation This means that it has to be finished before any new active can be performed Triggers that request an other power transition occurring a currently performed power trans...

Page 375: ...Bits Type Description SEQATRG 0 w Sequence A Trigger Setting this bit trigger a power transition defined by sequence A 0B No action 1B Sequence A is started Sequence A is only started if Sequence B is not currently active SEQBTRG 1 w Sequence B Trigger Setting this bit trigger a power transition defined by sequence B 0B No action 1B Sequence B is started Sequence B is only started if Sequence A is...

Page 376: ...WUT Trigger Enable This bit defines if an WUT event can trigger sequence B or not 0B Sequence B is never triggered by an WUT event 1B Sequence B is triggered by an WUT event ESR0EN 9 rw ESR0 Trigger Enable This bit defines if an ESR0 event can trigger sequence B or not 0B Sequence B is never triggered by an ESR0 event 1B Sequence B is triggered by ESR0 event ESR1EN 10 rw ESR1 Trigger Enable This b...

Page 377: ...s left unchanged 1B OSC_WU is disabled SEQBOSCDIS 14 rw Sequence B OSC_WU Disable This bit defines if the OSC_WU is disabled with the end of the sequence B 0B The enable setting for OSC_WU is left unchanged 1B OSC_WU is disabled GSCBY 15 rw GSC Bypass This bit defines if an PSC event can trigger GSC action or not 0B The normal GSC action is requested 1B No GSC action is started 0 7 5 12 r Reserved...

Page 378: ...CT A ACT r rh rh rh Field Bits Type Description AACT 0 rh Sequence A Active This bit indicates if currently sequence A is active or not 0B Sequence A is not active 1B Sequence A is active BACT 1 rh Sequence B Active This bit indicates if currently sequence B is active or not 0B Sequence B is not active 1B Sequence B is active RES 12 2 rh Reserved Value undefined 0 15 13 rw Reserved Read as 0 shoul...

Page 379: ...N1 CLK ENM V1 VM rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description VM 2 0 rwh DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested from EVR_M 000B Full Voltage with HP bandgap selected 001B Reduced Voltage with LPR selected 010B Reserved do not use this combination 011B Full Voltage with LPR selected 100B Off is configured 101B Off is configure...

Page 380: ... all clocks in the DMP_1 are disabled and DMP_1 is not longer powered 101B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B but DMP_1 is powered with EVR_1 configuration 110B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B all clocks in the DMP_1 are enabled 111B Configuration is unchanged readin...

Page 381: ...K 2 from PVC_M AND OK 1 from PVC_1 is used 1000BOK 2 from PVC_1 is used 1001BOK 1 from PVC_M AND OK 2 from PVC_1 is used 1010BOK 2 from PVC_M AND OK 2 from PVC_1 is used 1011BOK 1 from PVC_M AND OK 2 from PVC_M AND OK 2 from PVC_1 is used 1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is used 1101BOK 1 from PVC_M AND OK 1 from PVC_1 AND OK 2 from PVC_1 is used 1110BOK 2 from PVC_M AND OK 1 from PVC_1 AN...

Page 382: ...ed and delivers valid results 1B The PVC_M is disabled and deliver no valid results PVC1OFF 14 rwh PVC_1 Disabled This bit defines whether the PVC_1 generates any valid check results or not The PVC_1 can be disabled in order to save power 0B The PVC_1 is enabled and delivers valid results 1B The PVC_1 is disabled and deliver no valid results RES 15 rwh Reserved Read as 1 should be written with 1 T...

Page 383: ...EL CLK EN 1 CLK EN M V1 VM rw rw rw rw rw rw rw rw rw Field Bits Type Description VM 2 0 rw DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested with this step from EVR_M 000B Full Voltage with HP bandgap selected 001B Reduced Voltage with LPR selected 010B Reserved do not use this combination 011B Full Voltage with LPR selected 100B Off is configured 101B O...

Page 384: ...re disabled and DMP_1 is not longer powered 101B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B but DMP_1 is powered with EVR_1 configuration 110B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B all clocks in the DMP_1 are enabled 111B Configuration is unchanged reading returns last configured ...

Page 385: ...K 2 from PVC_M AND OK 1 from PVC_1 is used 1000BOK 2 from PVC_1 is used 1001BOK 1 from PVC_M AND OK 2 from PVC_1 is used 1010BOK 2 from PVC_M AND OK 2 from PVC_1 is used 1011BOK 1 from PVC_M AND OK 2 from PVC_M AND OK 2 from PVC_1 is used 1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is used 1101BOK 1 from PVC_M AND OK 1 from PVC_1 AND OK 2 from PVC_1 is used 1110BOK 2 from PVC_M AND OK 1 from PVC_1 AN...

Page 386: ... results 1B The PVC_M is disabled and deliver no valid results PVC1OFF 14 rw PVC_1 Disabled This bit defines whether the PVC generates any valid check results or not for this step The PVC can be disabled in order to save power 0B The PVC_1 is enabled and delivers valid results 1B The PVC_1 is disabled and deliver no valid results SEN 15 rw Step Enable This bit defines the operation that is connect...

Page 387: ...0H SEQASTEP6 Sequence Step 6 for Set A Register SFR FEF0H 78H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEN PVC 1 OFF PVC M OFF SYS DIV TRGSEL CLK EN 1 CLK EN M V1 VM rw rw rw rw rw rw rw rw rw Field Bits Type Description VM 2 0 rw DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested with this step from EVR_M 000B Full Voltage with HP bandgap s...

Page 388: ...re disabled and DMP_1 is not longer powered 101B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B but DMP_1 is powered with EVR_1 configuration 110B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B all clocks in the DMP_1 are enabled 111B Configuration is unchanged reading returns last configured ...

Page 389: ...K 2 from PVC_M AND OK 1 from PVC_1 is used 1000BOK 2 from PVC_1 is used 1001BOK 1 from PVC_M AND OK 2 from PVC_1 is used 1010BOK 2 from PVC_M AND OK 2 from PVC_1 is used 1011BOK 1 from PVC_M AND OK 2 from PVC_M AND OK 2 from PVC_1 is used 1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is used 1101BOK 1 from PVC_M AND OK 1 from PVC_1 AND OK 2 from PVC_1 is used 1110BOK 2 from PVC_M AND OK 1 from PVC_1 AN...

Page 390: ... results 1B The PVC_M is disabled and deliver no valid results PVC1OFF 14 rw PVC_1 Disabled This bit defines whether the PVC generates any valid check results or not for this step The PVC can be disabled in order to save power 0B The PVC_1 is enabled and delivers valid results 1B The PVC_1 is disabled and deliver no valid results SEN 15 rw Step Enable This bit defines the operation that is connect...

Page 391: ...EL CLK EN 1 CLK EN M V1 VM rw rw rw rw rw rw rw rw rw Field Bits Type Description VM 2 0 rw DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested with this step from EVR_M 000B Full Voltage with HP bandgap selected 001B Reduced Voltage with LPR selected 010B Reserved do not use this combination 011B Full Voltage with LPR selected 100B Off is configured 101B O...

Page 392: ...re disabled and DMP_1 is not longer powered 101B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B but DMP_1 is powered with EVR_1 configuration 110B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B all clocks in the DMP_1 are enabled 111B Configuration is unchanged reading returns last configured ...

Page 393: ...K 2 from PVC_M AND OK 1 from PVC_1 is used 1000BOK 2 from PVC_1 is used 1001BOK 1 from PVC_M AND OK 2 from PVC_1 is used 1010BOK 2 from PVC_M AND OK 2 from PVC_1 is used 1011BOK 1 from PVC_M AND OK 2 from PVC_M AND OK 2 from PVC_1 is used 1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is used 1101BOK 1 from PVC_M AND OK 1 from PVC_1 AND OK 2 from PVC_1 is used 1110BOK 2 from PVC_M AND OK 1 from PVC_1 AN...

Page 394: ... results 1B The PVC_M is disabled and deliver no valid results PVC1OFF 14 rw PVC_1 Disabled This bit defines whether the PVC generates any valid check results or not for this step The PVC can be disabled in order to save power 0B The PVC_1 is enabled and delivers valid results 1B The PVC_1 is disabled and deliver no valid results SEN 15 rw Step Enable This bit defines the operation that is connect...

Page 395: ...0H SEQBSTEP6 Sequence Step 6 for Set B Register SFR FEFEH 7FH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEN PVC 1 OFF PVC M OFF SYS DIV TRGSEL CLK EN 1 CLK EN M V1 VM rw rw rw rw rw rw rw rw rw Field Bits Type Description VM 2 0 rw DMP_M Voltage Configuration This bit defines the DMP_M core supply voltage that is requested with this step from EVR_M 000B Full Voltage with HP bandgap s...

Page 396: ...re disabled and DMP_1 is not longer powered 101B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B but DMP_1 is powered with EVR_1 configuration 110B Configuration is unchanged reading returns last configured value out of 000B 001B 010B 011B or 100B all clocks in the DMP_1 are enabled 111B Configuration is unchanged reading returns last configured ...

Page 397: ...K 2 from PVC_M AND OK 1 from PVC_1 is used 1000BOK 2 from PVC_1 is used 1001BOK 1 from PVC_M AND OK 2 from PVC_1 is used 1010BOK 2 from PVC_M AND OK 2 from PVC_1 is used 1011BOK 1 from PVC_M AND OK 2 from PVC_M AND OK 2 from PVC_1 is used 1100BOK 1 from PVC_1 AND OK 2 from PVC_1 is used 1101BOK 1 from PVC_M AND OK 1 from PVC_1 AND OK 2 from PVC_1 is used 1110BOK 2 from PVC_M AND OK 1 from PVC_1 AN...

Page 398: ... results 1B The PVC_M is disabled and deliver no valid results PVC1OFF 14 rw PVC_1 Disabled This bit defines whether the PVC generates any valid check results or not for this step The PVC can be disabled in order to save power 0B The PVC_1 is enabled and delivers valid results 1B The PVC_1 is disabled and deliver no valid results SEN 15 rw Step Enable This bit defines the operation that is connect...

Page 399: ... ESFR F020H 10H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L2 AS EN L2 RST EN L2 INT EN L2 A LEV 0 LEV2V L1 AS EN L1 RST EN L1 INT EN L1 A LEV 0 LEV1V rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description LEV1V 2 0 rw Level Threshold 1 Voltage Configuration This bit field defines the level of threshold 1 that is compared with the DMP_1 core voltage The values for the differe...

Page 400: ...evel Threshold 1 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison check was successful When a check is successful is defined via bit L1ALEV 0B No asynchronous actions are performed 1B Asynchronous actions can be performed LEV2V 10 8 rw Level 2 Voltage Configuration This bit field defines the level of threshold 2 that is compared with the DMP_1 c...

Page 401: ...vel Threshold 2 Reset Request Enable This bit defines if a reset request trigger is requested if the comparison check was successful When a check is successful is defined via bit L2ALEV 0B No reset is requested 1B An reset is requested L2ASEN 15 rw Level Threshold 2 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison check was successful When a che...

Page 402: ... Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L2 AS EN L2 RST EN L2 INT EN L2 A LEV 0 LEV2V L1 AS EN L1 RST EN L1 INT EN L1 A LEV 0 LEV1V rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description LEV1V 2 0 rw Level Threshold 1 Voltage Configuration This bit field defines the level of threshold 1 that is compared with the DMP_M core voltage The values for the different configuratio...

Page 403: ...Threshold 1 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison check was successful When a check is successful is defined via bit L1ALEV 0B No asynchronous actions are performed 1B Asynchronous actions can be performed LEV2V 10 8 rw Level Threshold 2 Voltage Configuration This bit field defines the level of threshold 2 that is compared with the DM...

Page 404: ...vel Threshold 2 Reset Request Enable This bit defines if a reset request trigger is requested if the comparison check was successful When a check is successful is defined via bit L2ALEV 0B No reset is requested 1B An reset is requested L2ASEN 15 rw Level Threshold 2 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison check was successful When a che...

Page 405: ... 6 Set B Register ESFR F02EH 17H Reset Value 0544H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L2 AS EN L2 RST EN L2 INT EN L2 A LEV 0 LEV2V L1 AS EN L1 RST EN L1 INT EN L1 A LEV 0 LEV1V rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description LEV1V 2 0 rw Level 1 Voltage Configuration This bit field defines the level that is used by the comparator 1 in the PVC The values for the different config...

Page 406: ...ASEN 7 rw Level 1 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison level check was successful When a check is successful is defined via bit L1ALEV 0B No asynchronous actions are performed 1B Asynchronous actions can be performed LEV2V 10 8 rw Level 2 Voltage Configuration This bit field defines the level that is used by the comparator 2 in the P...

Page 407: ...Level 2 Reset Request Enable This bit defines if a reset request trigger is requested if the comparison level check was successful When a check is successful is defined via bit L2ALEV 0B No reset is requested 1B An reset is requested L2ASEN 15 rw Level 2 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison level check was successful When a check is ...

Page 408: ...egister MEM F1FEH Reset Value 0544H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L2 AS EN L2 RST EN L2 INT EN L2 A LEV 0 LEV2V L1 AS EN L1 RST EN L1 INT EN L1 A LEV 0 LEV1V rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description LEV1V 2 0 rw Level 1 Voltage Configuration This bit field defines the level that is used by the comparator 1 in the PVC The values for the different configurations are li...

Page 409: ...ASEN 7 rw Level 1 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison level check was successful When a check is successful is defined via bit L1ALEV 0B No asynchronous actions are performed 1B Asynchronous actions can be performed LEV2V 10 8 rw Level 2 Voltage Configuration This bit field defines the level that is used by the comparator 2 in the P...

Page 410: ...Level 2 Reset Request Enable This bit defines if a reset request trigger is requested if the comparison level check was successful When a check is successful is defined via bit L2ALEV 0B No reset is requested 1B An reset is requested L2ASEN 15 rw Level 2 Asynchronous Action Enable This bit defines if asynchronous action can be performed if the comparison level check was successful When a check is ...

Page 411: ... begins when at least one request source asserts its trigger in order to request a mode change in the SoC If several requests are pending there is an arbitration mechanism that treats this issue Request triggers are not stored by the GSC therefore a trigger source has to assert its trigger until the trigger is no longer valid or needed A request trigger is kept asserted as long as either the reque...

Page 412: ...currently no command request is broadcast that is not received by all slaves Table 6 12 Connection of the Request Sources Request Source Priority PSCB exit 0 PSCB entry 1 PSCA exit 2 PSCA entry 3 OCDS exit 4 ESR0 5 ESR1 6 ESR2 7 WUT 8 ITC 9 GPT12E 10 SW1 11 SW2 12 OCDS entry 14 Table 6 13 Request Source and Command Request Coupling Request Source Command Description PSCB exit Wake up Normal Mode P...

Page 413: ...software trigger In particular the clock off command should be triggered by SW2 The usage of commands requested by hardware has to be done carefully Only hardware resources requesting Normal Mode should be selected If the software has detected a wake up then pending mode change requests can be removed by clearing the bits of the selected sources in GSCEN and then enabling the bits in GSCEN again I...

Page 414: ... a mode where the clock can be stopped This is done by sending a debug command Leaving the Suspend Mode should serve the goal that debugging is a non intrusive operation Therefore leaving the Suspend Mode can not lead to only one dedicated system mode instead it leads to the system mode the system left when it was requested to exit the Suspend Mode The system mode is stored when a Suspend Mode req...

Page 415: ...RG2 SWT RG1 r rwh rwh Field Bits Type Description SWTRG1 0 rwh Software Trigger 1 SW1 0B No SW1 request trigger is generated 1B A SW1 request trigger is generated This bit is automatically cleared if the SW1 request trigger wins the arbitration and was broadcast to the system SWTRG2 1 rwh Software Trigger 2 SW2 0B No SW2 request trigger is generated 1B A SW2 request trigger is generated This bit i...

Page 416: ... into account enabled PSCBENEN 1 rw PSC Sequence B Entry Request Trigger Enable 0B PSC sequence B entry request trigger is not taken into account disabled 1B PSC sequence B entry request trigger is taken into account enabled PSCAEXEN 2 rw PSC Sequence A Exit Request Trigger Enable 0B PSC sequence A exit request trigger is not taken into account disabled 1B PSC sequence A exit request trigger is ta...

Page 417: ...t disabled 1B ESR2 request trigger is taken into account enabled WUTEN 8 rw WUT Request Trigger Enable 0B WUT request trigger is not taken into account disabled 1B WUT request trigger is taken into account enabled ITCEN 9 rw ITC Request Trigger Enable 0B ITC request trigger is not taken into account disabled 1B ITC request trigger is taken into account enabled GPTEN 10 rw GTP12E Request Trigger En...

Page 418: ...is taken into account enabled RES1 13 rw Reserved Read as 1 after reset returns the value that is written OCDSENEN 14 rw OCDS Entry Request Trigger Enable 0B OCDS entry request trigger is not taken into account disabled 1B OCDS entry request trigger is taken into account enabled OCDS entry is the request source belonging to the according connector interface 0 15 r Reserved Read as 0 should be writ...

Page 419: ...ld states the currently used system mode NEXT 5 4 rh Next to use Command This bit field states the next to be used system mode ERR 8 rh Error Status Flag This bit flags if with the last command that was broadcast was acknowledge with at least one error This bit is automatically cleared when a new command is broadcast PEN 9 rh Command Pending Flag This flag states if currently a command is pending ...

Page 420: ...at triggered the last request 0000B PSCB exit 0001B PSCB entry 0010B PSCA exit 0011B PSCA entry 0100B OCDS exit 0101B ESR0 0110B ESR1 0111B ESR2 1000B WUT 1001B ITC 1010B GPT12E 1011B SW1 1100B SW2 1101B Reserved do not use this combination 1110B OCDS entry 1111B Reserved do not use this combination 0 3 2 7 6 15 14 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 421: ...p Status Register Register STSTAT contains the information required by the boot software to identify the different start up settings that can be selected STSTAT Start up Status Register MEM F1E0H Reset Value 8000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 HWCFG r r rh Field Bits Type Description HWCFG 7 0 rh Hardware Configuration Setting This bit field contains the value that is used by the boot ...

Page 422: ...t Channels y for combination of events definition of their effects and distribution to the system interrupt generation ADC conversion triggers Figure 6 22 External Request Unit Overview These tasks are handled by the following building blocks An External Request Select Unit ERSx per Input Channel allows the selection of one out of two or a logical combination of two input signals ERU_xA ERU_xB to ...

Page 423: ...g CC2 are made available and can be combined with the triggers generated by the Input Channels of the ERU An Output Gating Unit OGUy per Output Channel that combines the available trigger events and status information from the Input Channels An event of one Input Channel can lead to reactions of several Output Channels or also events of several Input Channels can be combined to a reaction of one O...

Page 424: ... ERS0 ERU_0A0 ERU_0A1 ERU_0A2 ERU_0A3 ERU_0B0 ERU_0B1 ERU_0B2 ERU_0B3 ESR1 ERU_1A0 ERU_1A1 ERU_1A2 ERU_1A3 ERU_1B0 ERU_1B1 ERU_1B2 ERU_1B3 P2 1 P1 0 P5 13 P2 2 P1 1 ESR2 ERU_2A0 ERU_2A1 ERU_2A2 ERU_2A3 ERU_2B0 ERU_2B1 ERU_2B2 ERU_2B3 MultiCAN_CAN3INS selected receive input CAN3 ERU_3A0 ERU_3A1 ERU_3A2 ERU_3A3 ERU_3B0 ERU_3B1 ERU_3B2 ERU_3B3 P1 2 P1 3 reserved reserved reserved reserved ERS1 ERS2 E...

Page 425: ...ction of the input is made within the respective USIC or MultiCAN module Usually such signals would be selected for an ERU function when the input function to the USIC or MultiCAN module is not used otherwise or the module is not used at all However it is also possible to select a input which is actually needed in a USIC or MultiCAN module and to use it also in the ERU to provide for certain trigg...

Page 426: ...an only be correctly detected if both the high phase and the low phase of the input are each longer than 1 fSYS Table 6 14 ERSx Connections in XC2200 Input from to Module I O to ERSx Can be used to as ERS0 Inputs ERU_0A0 P2 1 I ERS0 input A ERU_0A1 ESR1 I ERU_0A2 U0C0_DX0INS I ERU_0A3 U0C0_DX2INS I ERU_0B0 P1 0 I ERS0 input B ERU_0B1 P5 13 I ERU_0B2 U0C1_DX0INS I ERU_0B3 U0C1_DX2INS I ERS1 Inputs ...

Page 427: ...B ERU_2B1 MultiCAN_CAN2INS I ERU_2B2 U2C1_DX0INS I ERU_2B3 U2C1_DX2INS I ERS3 Inputs ERU_3A0 P1 3 I ERS3 input A ERU_3A1 MultiCAN_CAN1INS I ERU_3A2 0 I ERU_3A3 0 I ERU_3B0 U1C0_DX1INS I ERS3 input B ERU_3B1 MultiCAN_CAN0INS I ERU_3B2 0 I ERU_3B3 0 I Table 6 14 ERSx Connections in XC2200 cont d Input from to Module I O to ERSx Can be used to as ...

Page 428: ... ERU_xB 3 0 In addition to the direct choice of either input Ax or Bx or their inverted values the possible logical combinations for two selected inputs are a logical AND or a logical OR Figure 6 25 External Request Select Unit Overview The ERS units are controlled via register EXISEL one register for all four ERSx units and registers EXICONx one register for each ERSx and associated ETLx unit e g...

Page 429: ...s detected the status flag EXICONx FL becomes set This flag can also be modified by software set or clear Two different operating modes are supported by this status flag It can be used as sticky flag that is set by hardware when the desired event has been detected and has to be cleared by software In this operating mode it indicates that the event has taken place but without indicating the actual ...

Page 430: ...g Units OGUy in parallel see Figure 6 27 to provide pattern detection capability of all OGUy units based on different or the same status flags In addition to the modification of the status flag a trigger pulse output TRxy of ETLx can be enabled by bit EXICONx PE and selected to trigger actions in one of the OGUy units The target OGUy for the trigger is selected by bit field EXICON OCS The trigger ...

Page 431: ... the OGUy units Figure 6 27 Connecting Matrix between ETLx and OGUy OGU0 ERU_ETL_OGU_Overview vsd ETL0 ETL1 ETL2 ETL3 TR00 TR01 TR02 TR03 EXICON0 FL TR10 TR11 TR12 TR13 EXICON1 FL TR20 TR21 TR22 TR23 EXICON2 FL TR30 TR31 TR32 TR33 EXICON3 FL Pattern Detection Inputs Trigger Inputs TRx0 OGU1 Pattern Detection Inputs Trigger Inputs TRx1 OGU3 Pattern Detection Inputs Trigger Inputs TRx3 OGU2 Pattern ...

Page 432: ...d to OGUy a selected peripheral related trigger event and a pattern change event if enabled are logically OR combined Pattern detection see Section 6 8 6 2 The status flags EXICONx FL of the Input Channels can be enabled to take part in the pattern detection A pattern match is detected while all enabled status flags are set Figure 6 28 Output Gating Unit for Output Channel y ERU_OGU vsd Output Gat...

Page 433: ...nnels the trigger output TRxy can be enabled and the trigger event can be directed to one of the OGUy units One out of three peripheral trigger signals per OGUy can be selected as additional trigger source These peripheral triggers are generated by on chip peripheral modules such as capture compare or timer units The selection is done by bit field EXOCONy ISS In the case that at least one pattern ...

Page 434: ...uded in the pattern detection are 1 Pattern miss EXOCONy PDR 0 and ERU_PDOUTy 0 A pattern miss is indicated while at least one of the status flags FL that are included in the pattern detection is 0 Table 6 15 OGUy Peripheral Trigger Connections in XC2200 Input from to Module I O to OGUy Can be used to as OGU0 Inputs ERU_OGU01 CCU60_MCM_ST I Peripheral triggers for OGU0 ERU_OGU02 CCU60_T13_PM I ERU...

Page 435: ...compare unit is selected while a combination of input signals occurs pattern detection based on ETLx status bits A programmable gating scheme introduces flexibility to adapt to application requirements and allows the generation of interrupt requests ERU_IOUTy under different conditions Pattern match EXOCONy GP 10B An interrupt request is issued when a trigger event occurs while the pattern detecti...

Page 436: ...output ERU_GOUT0 ADC0 REQGT0A ADC0 REQGT1A ADC0 REQGT2A ADC1 REQGT0A ADC1 REQGT1A ADC1 REQGT2A O Gated pattern detection output ERU_TOUT0 not connected O Trigger output ERU_IOUT0 ITC CC2_CC16IC O Interrupt output OGU1 Outputs ERU_PDOUT1 not connected O Pattern detection output ERU_GOUT1 ADC0 REQGT0B ADC0 REQGT1B ADC0 REQGT2B ADC1 REQGT0B ADC1 REQGT1B ADC1 REQGT2B O Gated pattern detection output E...

Page 437: ...ERU_IOUT2 ITC CC2_CC18IC O Interrupt output OGU3 Outputs ERU_PDOUT3 not connected O Pattern detection output ERU_GOUT3 not connected O Gated pattern detection output ERU_TOUT3 not connected O Trigger output ERU_IOUT3 ITC CC2_CC19IC O Interrupt output Table 6 16 ERU Output Connections in XC2200 cont d Output from to Module I O to OGUy Can be used to as ...

Page 438: ...ted for A0 00B Input ERU_0A0 is selected 01B Input ERU_0A1 is selected 10B Input ERU_0A2 is selected 11B Input ERU_0A3 is selected EXS0B 3 2 rw External Source Select for B0 ERS0 This bit field defines which input is selected for B0 00B Input ERU_0B0 is selected 01B Input ERU_0B1 is selected 10B Input ERU_0B2 is selected 11B Input ERU_0B3 is selected EXS1A 5 4 rw External Source Select for A1 ERS1...

Page 439: ...t is selected for B2 00B Input ERU_2B0 is selected 01B Input ERU_2B1 is selected 10B Input ERU_2B2 is selected 11B Input ERU_2B3 is selected EXS3A 13 12 rw External Source Select for A3 ERS3 This bit field defines which input is selected for A3 00B Input ERU_3A0 is selected 01B Input ERU_3A1 is selected 10B Input ERU_3A2 is selected 11B Input ERU_3A3 is selected EXS3B 15 14 rw External Source Sele...

Page 440: ...ESFR F032H 19H Reset Value 0000H EXICON2 External Input Control 2 Register ESFR F034H 1AH Reset Value 0000H EXICON3 External Input Control 3 Register ESFR F036H 1CH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NB NA SS FL OCS FE RE LD PE r rw rw rw rwh rw rw rw rw rw Field Bits Type Description PE 0 rw Output Trigger Pulse Enable for ETLx This bit enables the generation of an output t...

Page 441: ... status flag FL or as possible trigger pulse for TRxy 0B A rising edge is not considered as edge event 1B A rising edge is considered as edge event FE 3 rw Falling Edge Detection Enable ETLx This bit enables disables the falling edge event as edge event as set condition for the status flag FL or as possible trigger pulse for TRxy 0B A falling edge is not considered as edge event 1B A falling edge ...

Page 442: ...combination 01B Input B without additional combination 10B Input A OR input B 11B Input A AND input B NA 10 rw Input A Negation Select for ERSx This bit selects the polarity for the input A 0B Input A is used directly 1B Input A is inverted NB 11 rw Input B Negation Select for ERSx This bit selects the polarity for the input B 0B Input B is used directly 1B Input B is inverted 0 15 12 r Reserved R...

Page 443: ... IPEN 2 IPEN 1 IPEN 0 0 GP PDR GE EN ISS rw rw rw rw r rw rh rw rw Field Bits Type Description ISS 1 0 rw Internal Trigger Source Selection This bit field defines which input is selected as peripheral trigger input for OGUy The possible input signals are given in Table 6 15 00B The peripheral trigger function is disabled 01B Input ERU_OGUy1 is selected 10B Input ERU_OGUy2 is selected 11B Input ERU...

Page 444: ...s equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected pattern match PDR 1 11B ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected pattern miss PDR 0 IPENx x 0 3 12 x rw Pattern Detection Enable for ETLx Bit IPENx defines whether the trigger...

Page 445: ...onnected to the same interrupt node pointer in register INTNPx the requests are combined to one common line Interrupt Node Assignment The interrupt sources of the SCU module can be mapped to the dedicated interrupt node 6CH or 6BH by programming the interrupt node pointer registers INTNP0 and INTNP1 The default assignment of the interrupt sources to the nodes and their corresponding control regist...

Page 446: ...red after the identified request has been handled To clear an interrupt request that is stored in register DMPMIT first clear the request source of the source e g WUTRG clear the request within DMP_M via DMPMITCLR and then clear the request within DMP_1 via INTCLR 6 9 2 SCU Interrupt Sources The SCU receives the interrupt request lines listed in Table 6 17 Table 6 17 SCU Interrupt Overview Source ...

Page 447: ... Field Bits Type Description SWDI1 0 rh SWD Interrupt Request Flag 1 This bit is set if bit DMPMIT SWDI1 is set 0B No SWDI1 interrupt trigger has occured since this bit was cleared the last time 1B A SWDI1 interrupt trigger has occured since this bit was cleared the last time SWDI2 1 rh SWD Interrupt Request Flag 2 This bit is set if bit DMPMIT SWDI2 is set 0B No SWDI2 interrupt trigger has occure...

Page 448: ...he last time 1B A PVC1I2 interrupt trigger has occured since this bit was cleared the last time WUTI 6 rh Wake up Timer Trim Interrupt Request Flag This bit is set if the WUT trim trigger event occur and bit is INTDIS WUTI 0 0B No WUT interrupt trigger has occured since this bit was cleared the last time 1B A WUT interrupt trigger has occured since this bit was cleared the last time WUI 7 rh Wake ...

Page 449: ...rupt Request Flag This bit is set if the GSC error bit is set and bit is INTDIS GSCI 0 0B No GSC interrupt trigger has occured since this bit was cleared the last time 1B A GSC interrupt trigger has occured since this bit was cleared the last time 0 15 10 rh Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 450: ...pt Request Flag 1 0B No action 1B Bit INTSTAT SWDI1 is cleared SWDI2 1 w Clear SWD Interrupt Request Flag 2 0B No action 1B Bit INTSTAT SWDI2 is cleared PVCMI1 2 w Clear PVC_M Interrupt Request Flag 1 0B No action 1B Bit INTSTAT PVCMI1 is cleared PVCMI2 3 w Clear PVC_M Interrupt Request Flag 2 0B No action 1B Bit INTSTAT PVCMI2 is cleared PVC1I1 4 w Clear PVC_1 Interrupt Request Flag 1 0B No actio...

Page 451: ... 6 191 V2 1 2008 08 SCU V1 13 WDTI 8 w Clear Watchdog Timer Interrupt Request Flag 0B No action 1B Bit INTSTAT WDTI is cleared GSCI 9 w Clear GSC Interrupt Request Flag 0B No action 1B Bit INTSTAT GSCI is cleared 0 15 10 w Reserved Must be written with 0 Field Bits Type Description ...

Page 452: ... 0 w Set SWD Interrupt Request Flag 1 0B No action 1B Bit INTSTAT SWDI1 is set SWDI2 1 w Set SWD Interrupt Request Flag 2 0B No action 1B Bit INTSTAT SWDI2 is set PVCMI1 2 w Set PVC_M Interrupt Request Flag 1 0B No action 1B Bit INTSTAT PVCMI1 is set PVCMI2 3 w Set PVC_M Interrupt Request Flag 2 0B No action 1B Bit INTSTAT PVCMI2 is set PVC1I1 4 w Set PVC_1 Interrupt Request Flag 1 0B No action 1B...

Page 453: ...Manual 6 193 V2 1 2008 08 SCU V1 13 WDTI 8 w Set Watchdog Timer Interrupt Request Flag 0B No action 1B Bit INTSTAT WDTI is set GSCI 9 w Set GSC Interrupt Request Flag 0B No action 1B Bit INTSTAT GSCI is set 0 15 10 w Reserved Must be written with 0 Field Bits Type Description ...

Page 454: ...w Disable SWD Interrupt Request 2 0B SWDI2 interrupt request enabled 1B SWDI2 interrupt request disabled PVCMI1 2 rw Disable PVC_M Interrupt Request 1 0B PVCMI1 interrupt request enabled 1B PVCMI1 interrupt request disabled PVCMI2 3 rw Disable PVC_M Interrupt Request 2 0B PVCMI2 interrupt request enabled 1B PVCMI2 interrupt request disabled PVC1I1 4 rw Disable PVC_1 Interrupt Request 1 0B PVC1I1 i...

Page 455: ... V1 13 WDTI 8 rw Disable Watchdog Timer Interrupt Request 0B WDT interrupt request enabled 1B WDT interrupt request disabled GSCI 9 rw Disable GSC Interrupt Request 0B GSC interrupt request enabled 1B GSC interrupt request disabled 0 15 10 rw Reserved Should be written with 0 Field Bits Type Description ...

Page 456: ...S SWDI1 00B Interrupt node 6CH is selected 01B Interrupt node 6BH is selected 10B Reserved do not use this combination 11B Reserved do not use this combination SWD2 3 2 rw Interrupt Node Pointer for SWD 2 Interrupts This bit field defines the interrupt node which is requested due to the set condition for bit INTSTAT SWDI2 if enabled by bit INTDIS SWDI2 00B Interrupt node 6CH is selected 01B Interr...

Page 457: ...de Pointer for PVC_1 2 Interrupts This bit field defines the interrupt node which is requested due to the set condition for bit INTSTAT PCV1I2 if enabled by bit INTDIS PVC1I2 00B Interrupt node 6CH is selected 01B Interrupt node 6BH is selected 10B Reserved do not use this combination 11B Reserved do not use this combination WUT 13 12 rw Interrupt Node Pointer for WU Trim Interrupts This bit field...

Page 458: ...equested due to the set condition for bit INTSTAT WDTI if enabled by bit INTDIS WDTI 00B Interrupt node 6CH is selected 01B Interrupt node 6BH is selected 10B Reserved do not use this combination 11B Reserved do not use this combination GSC 3 2 rw Interrupt Node Pointer for GSC Interrupts This bit field defines the interrupt node which is requested due to the set condition for bit INTSTAT GSCI if ...

Page 459: ...red and SWDCON0 L1ACON 01B and INTDIS SWDI1 0 0B No SWDI1 interrupt was requested since this bit was cleared the last time 1B A SWDI1 interrupt was requested since this bit was cleared the last time SWDI2 1 rh SWD Interrupt Request Flag 2 This bit is set if bit SWDCON0 L2OK is cleared and SWDCON0 L2ACON 01B and INTDIS SWDI2 0 0B No SWDI2 interrupt was requested since this bit was cleared the last ...

Page 460: ...is bit was cleared the last time PVC1I2 5 rh PVC_1 Interrupt Request Flag 2 This bit is set if bit PVC1CON0 LEV2OK is cleared and PVC1CON0 L2INTEN 1B and INTDIS PVC1I2 0 0B No PVC1I2 interrupt was requested since this bit was cleared the last time 1B A PVC1I2 interrupt was requested since this bit was cleared the last time WUTI 6 rh Wake up Trim Interrupt Request Flag This bit is set if a wake up ...

Page 461: ...SR1T 12 rh ESR1 Trap Request Flag This bit is set if pin ESR1 is asserted 0B No ESR1 trap was requested since this bit was cleared the last time 1B An ESR1 trap was requested since this bit was cleared the last time ESR2T 13 rh ESR2 Trap Request Flag This bit is set if pin ESR2 is asserted 0B No ESR2 trap was requested since this bit was cleared the last time 1B An ESR2 trap was requested since th...

Page 462: ... Type Description SWDI1 0 w Clear SWD1 Interrupt Request Flag 1 0B No action 1B Bit DMPMIT SWDI1 is cleared SWDI2 1 w Clear SWD Interrupt Request Flag 2 0B No action 1B Bit DMPMIT SWDI2 is cleared PVCMI1 2 w Clear PVC_M Interrupt Request Flag 1 0B No action 1B Bit DMPMIT PVCMI1 is cleared PVCMI2 3 w Clear PVC_M Interrupt Request Flag 2 0B No action 1B Bit DMPMIT PVCMI2 is cleared PVC1I1 4 w Clear ...

Page 463: ...r ESR0 Trap Request Flag 0B No action 1B Bit DMPMIT ESR0T is cleared ESR1T 12 w Clear ESR1 Trap Request Flag 0B No action 1B Bit DMPMIT ESR1T is cleared ESR2T 13 w Clear ESR2 Trap Request Flag 0B No action 1B Bit DMPMIT ESR2T is cleared RAT 15 w Clear Register Access Trap Request Flag 0B No action 1B Bit DMPMIT RAT is cleared 0 10 9 14 r Reserved Read as 0 should be written with 0 Field Bits Type ...

Page 464: ... selected ISS1 1 rw Interrupt Source Select for CC2_CC17IC 0B CC2 channel 17 interrupt is selected 1B External interrupt request ERU_IOUT1 is selected ISS2 2 rw Interrupt Source Select for CC2_CC18IC 0B CC2 channel 18 interrupt is selected 1B External interrupt request ERU_IOUT2 is selected ISS3 3 rw Interrupt Source Select for CC2_CC19IC 0B CC2 channel 19 interrupt is selected 1B External interru...

Page 465: ...rupt request ERU_IOUT2 is selected ISS11 11 rw Interrupt Source Select for CC2_CC27IC 0B CC2 channel 27 interrupt is selected 1B External interrupt request ERU_IOUT3 is selected ISS12 12 rw Interrupt Source Select for CC2_CC28IC 0B CC2 channel 28 interrupt is selected 1B USIC2 channel 0 SR3 is selected ISS13 13 rw Interrupt Source Select for CC2_CC29IC 0B CC2 channel 29 interrupt is selected 1B US...

Page 466: ...us TCLR THCOUNT is updated after every count cycle while the temperature compensation is enabled Software can compare the temperature related count value TCLR THCOUNT to several thresholds temperature levels in order to determine the control values TCCR TCC Figure 6 30 Temperature Compensation Clock Generation The clock divider is programmed via bit field TCCR TCDIV The value that should be used f...

Page 467: ...es not generate temperature compensation values continously The idea is that the SW frequently updates the pad control with the value currently found in the tempcomp register e g by an interrupt generated by a timer Since temparature is a continous function it is not relevant whether the temperature value read is new or the value of a previous meaurement ...

Page 468: ...ature Compensation Control The value which controls the temperature compensation inputs of the pads 00B Maximum reduction min driver strength i e very low temperature 11B No reduction max driver strength i e very high temperature TCDIV 6 2 rw Temperature Compensation Clock Divider This value adjusts the temperature compensation logic to the selected operating frequency TCE 7 rw Temperature Compens...

Page 469: ... stop at count 255 TCLR Temperature Comp Level Register ESFR F0ACH 56H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 THCOUNT r rh Field Bits Type Description THCOUNT 7 0 rh Threshold Counter Returns the result of the most recent count cycle of the temperature sensor to be compared with the thresholds 0 15 8 r Reserved Read as 0 should be written with 0 ...

Page 470: ...ecure way to detect and recover from software or hardware failure The WDT helps to abort an accidental malfunction of the XC2200 in a user specified time period When enabled the WDT will cause the XC2200 system to be reset if the WDT is not serviced within a user programmable time period The CPU must service the WDT within this time interval to prevent the WDT from causing a WDT reset request trig...

Page 471: ...REL RELV default value FFFCH for the calculation of the period in Normal Mode or the fixed value FFFFH for the calculation of the period in Prewarning Mode WDT Timer Reload The counter is reloaded and the prescaler is cleared when one of the following conditions occurs A successful access to register WDTREL The WDT is serviced via instruction SRVWDT A WDT overflow condition Prewarning Mode is ente...

Page 472: ...re the counter overflows Servicing is performed by the CPU via instructions SRVWDT and or ENWDT If the WDT is not serviced before the timer overflows a system malfunction is assumed and following operations are done An WDT interrupt trigger is issued Prewarning Mode is entered WDT Reset Trigger STMEM0 WDTCSOE 1 Normal Mode Disable Mode ENWDT Internal Application Reset Timer overflow DISWDT WDT_mod...

Page 473: ... processing before the coming reset In Prewarning Mode the WDT starts counting from FFFFH upwards and then requests a WDT reset on the overflow of the WDT from FFFFH to 0000H A reset request of the type as configured in RSTCON1 WDT can not be avoided No reset will be requested If RSTCON1 WDT is cleared The WDT does not react anymore to accesses to its registers and to the ENWDT or DISWDT instructi...

Page 474: ...te application software has to clear STMEM0 WDTCSOE too Note After the double WDT reset request trigger is generated the counter is stopped after the overflow Port Configuration during WDT Reset The behavior of the ESRx ports can be defined with respect to the reset type by bit field ESRCFGx PC For the coding of PC see Table 6 9 The allows to signal the occurence of a reset The configuration of th...

Page 475: ...Kernel Registers 6 11 4 1 WDT Reload Register This register defines the WDT reload value WDTREL WDT Reload Register ESFR F0C8H 64H Reset Value FFFCH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RELV rw Field Bits Type Description RELV 15 0 rw Reload Value for the Watchdog Timer This bit field defines the reload value for the WDT ...

Page 476: ...ware when the Watchdog Timer overflows from FFFFH to 0000H This bit is only cleared through any Power on Reset an executed SRVWDT or ENWDT instruction Note It is not possible to clear this bit in Prewarning Mode with the SRVWDT or ENWDT instruction DS 1 rh Timer Enable Disable Status Flag 0B Timer is enabled default after reset 1B Timer is disabled This bit is cleared when instruction ENWDT was ex...

Page 477: ...uest to set input frequency to fIN 16384 1B Request to set input frequency to fIN 256 An update of this bit is taken into account after the next successful execution of instruction SRVWDT or ENWDT on a write to register WDTREL and always when the WDT is in Disable Mode 0 7 3 15 9 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 478: ...s Manual 6 218 V2 1 2008 08 SCU V1 13 6 11 4 3 WDT Timer Register WDTTIM WDT Timer Register ESFR F0CAH 65H Reset Value FFFCH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIM rh Field Bits Type Description TIM 15 0 rh Timer Value Reflects the current contents of the Watchdog Timer ...

Page 479: ...rap source is connected to the same trap via register TRAPNP the requests are combined to one common line Trap Node Assignment The trap sources of the system can be mapped to three trap nodes by programming the trap node pointer register TRAPNP The default assignment of the trap sources to the nodes and their corresponding control register is listed in Table 6 19 6 12 1 Trap Support Some of the tr...

Page 480: ...e identified request has been handled To clear a trap request that is stored in register DMPMIT first clear the request source of the source clear the request within DMP_M via DMPMITCLR and then clear the request within DMP_1 via TRAPCLR 6 12 2 SCU Trap Sources The SCU receives the trap lines listed in Table 6 19 Table 6 19 SCU Trap Request Overview Source of Trap Short Name Sticky Flag in DMPMIT ...

Page 481: ...FAT 0 rh Flash Access Trap Request Flag TRAPSTAT FAT is set when a flash access violation occurs and TRAPDIS FAT 0 0B No FA trap trigger has occured since this bit was cleared the last time 1B A FA trap trigger has occured since this bit was cleared the last time ESR0T 1 rh ESR0 Trap Request Flag TRAPSTAT ESR0T is set when bit DMPMIT ESR0T is set and TRAPDIS ESR0T 0 0B No ESR0 trap trigger has occ...

Page 482: ...ster Access Trap Request Flag TRAPSTAT RAT is set when bit DMPMIT RAT is set and TRAPDIS RAT 0 0B No RA trap trigger has occured since this bit was cleared the last time 1B A RA trap trigger has occured since this bit was cleared the last time PET 6 rh Parity Error Trap Request Flag TRAPSTAT PET is set when a memory parity error occurs and TRAPDIS PET 0 0B No PE trap trigger has occured since this...

Page 483: ...AT 0 w Clear Flash Access Trap Request Flag 0B No action 1B Flag TRAPSTAT FAT is cleared ESR0T 1 w Clear ESR0 Trap Request Flag 0B No action 1B Flag TRAPSTAT ESR0T is cleared ESR1T 2 w Clear ESR1 Trap Request Flag 0B No action 1B Flag TRAPSTAT ESR1T is cleared ESR2T 3 w Clear ESR2 Trap Request Flag 0B No action 1B Flag TRAPSTAT ESR2T is cleared OSCWDTT 4 w Clear OSCWDT Trap Request Flag 0B No acti...

Page 484: ...XC2200 Derivatives System Units Vol 1 of 2 System Control Unit SCU User s Manual 6 224 V2 1 2008 08 SCU V1 13 0 15 8 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 485: ...its Type Description FAT 0 w Set Flash Access Trap Request Flag 0B No action 1B Flag TRAPSTAT FAT is set ESR0T 1 w Set ESR0 Trap Request Flag 0B No action 1B Flag TRAPSTAT ESR0T is set ESR1T 2 w Set ESR1 Trap Request Flag 0B No action 1B Flag TRAPSTAT ESR1T is set ESR2T 3 w Set ESR2 Trap Request Flag 0B No action 1B Flag TRAPSTAT ESR2T is set OSCWDTT 4 w Set OSCWDT Trap Request Flag 0B No action 1...

Page 486: ...XC2200 Derivatives System Units Vol 1 of 2 System Control Unit SCU User s Manual 6 226 V2 1 2008 08 SCU V1 13 0 15 8 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 487: ...w Disable Flash Access Trap Request 0B FA trap request enabled 1B FA trap request disabled ESR0T 1 rw Disable ESR0 Trap Request 0B ESR0 trap request enabled 1B ESR0 trap request disabled ESR1T 2 rw Disable ESR1 Trap Request 0B ESR1 trap request enabled 1B ESR1 trap request disabled ESR2T 3 rw Disable ESR2 Trap Request 0B ESR2 trap request enabled 1B ESR2 trap request disabled OSCWDTT 4 rw Disable ...

Page 488: ...XC2200 Derivatives System Units Vol 1 of 2 System Control Unit SCU User s Manual 6 228 V2 1 2008 08 SCU V1 13 0 15 8 r Reserved Read as 0 should be written with 0 Field Bits Type Description ...

Page 489: ... 00B Select request output SCU_TRQ0 TFR ACER 01B Select request output SCU_TRQ1 TFR SR1 10B Select request output SCU_TRQ2 TFR SR0 11B Reserved do not use this combination ESR0 3 2 rw Trap Node Pointer for ESR0 Traps TRAPNP ESR0 selects the trap request output for an enabled ESR0 trap request 00B Select request output SCU_TRQ0 TFR ACER 01B Select request output SCU_TRQ1 TFR SR1 10B Select request ...

Page 490: ...Trap Node Pointer for Register Access Traps TRAPNP RA selects the trap request output for an enabled RAT trap request 00B Select request output SCU_TRQ0 TFR ACER 01B Select request output SCU_TRQ1 TFR SR1 10B Select request output SCU_TRQ2 TFR SR0 11B Reserved do not use this combination PE 13 12 rw Trap Node Pointer for Parity Error Traps TRAPNP PE selects the trap request output for an enabled P...

Page 491: ...s not considered here Parity Checking is provided 6 13 1 Parity Error Handling The on chip RAM modules check parity information during read accesses and in case of an error a signal can be generated if enabled These signals are combined and trigger a trap If a parity error is detected during the trap handler routine a reset request trigger is generated Register PECON controls the behavior of parit...

Page 492: ...te the Access Error trap ACER The parity reset request trigger p_rst_req is generated when a parity error trap is request AND flag TFR ACER is set parity_error_MR PMTSR PESEN DSRAM PSRAM SBRAM MCRAM U0RAM Parity error U2RAM PECON PEENU2 PECON PEENU1 PECON PEENU0 PECON PEENSB PECON PEENPS PECON PEENDS PECON PEENDP PECON PEFU1 PECON PEFU0 PECON PEFMC PECON PEFSB PECON PEFPS PECON PEFDS PECON PEFDP 1...

Page 493: ...l software test update has to be enabled with bit PMTSR MTEx for each memory individually Otherwise a write to the parity control has no effect With each read access to a memory the parity from the memory parity control is stored in register PMTPR PRD The width and therefore the valid bits in register PMTPR is listed in Table 6 20 Test software should be located in external memory and should be wr...

Page 494: ... trap is requested for dual port memory parity errors 1B A Parity trap is requested for dual port memory parity errors PEENDS 1 rw Parity Error Trap Enable for Data SRAM 0B No Parity trap is requested for data SRAM parity errors 1B A Parity trap is requested for data SRAM parity errors PEENPS 2 rw Parity Error Trap Enable for Program SRAM 0B No Parity trap is requested for program SRAM parity erro...

Page 495: ...PEFDP 8 rwh Parity Error Flag for Dual Port Memory 0B No Parity errors have been detected for dual port memory 1B A Parity error is indicated and can trigger a trap request trigger if enabled for dual port memory The bit is only set by the enabled parity error from the dual port memory This bit can only be cleared via software Writing a zero to this bit does not change the content Writing a one to...

Page 496: ...This bit can only be cleared via software Writing a zero to this bit does not change the content Writing a one to this bit does clear the bit PEFU1 12 rwh Parity Error Flag for USIC1 Memory 0B No Parity errors have been detected for USIC1 memory 1B A Parity error is indicated and can trigger a trap request trigger if enabled for USIC1 memory The bit is only set by the enabled parity error from the...

Page 497: ...y This bit can only be cleared via software Writing a zero to this bit does not change the content Writing a one to this bit does clear the bit PEFSB 15 rwh Parity Error Flag for Standby Memory 0B No Parity errors have been detected for Standby memory 1B A Parity error is indicated and can trigger a trap request trigger if enabled for Standby memory The bit is only set by the enabled parity error ...

Page 498: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRD PWR rh rw Field Bits Type Description PRD 15 8 rh Parity Read Values for Memory Test For each byte of a memory module the parity bits generated during the most recent read access are indicated here PWR 7 0 rw Parity Write Values for Memory Test For each byte of a memory module the parity bits corresponding to the next write access are stored here ...

Page 499: ...Enable Control for Data SRAM Controls the test multiplexer for the data SRAM 0B Standard operation 1B Test parity bits used from PMTPR MTENPS 2 rw Memory Test Enable Control for Program SRAM Controls the test multiplexer for the program SRAM 0B Standard operation 1B Test parity bits used from PMTPR MTENSB 7 rw Memory Test Enable Control for Standby Memory Controls the test multiplexer for the Stan...

Page 500: ...ters are locked against any write access Write accesses have no effect on these registers This mode is entered automatically after the EINIT instruction is executed Secured Mode Protected registers can be written using a special command Registers that are protected by this mode are marked in Table 6 23 as Sec protected Access in Secured Mode can be achieved by preceding the intended write access w...

Page 501: ...ional to normal access parameters e g read only bit type r or rh the access limitations defined by the selected security level Independently of the security level all protected registers can also be read 6 14 1 1 Controlling the Security Level The two registers Security Level Command register SLC and Security Level Status register SLS control the security level The SLC register accepts the command...

Page 502: ...ew security level and or a new password Note It is recommended to lock all command sequences with an atomic sequence Table 6 21 Commands for Security Level Control Command Definition Note Command 0 AAAAH Command 1 5554H Command 2 96H 1 inverse password 1 denotes a bit field concatenation Command 3 000B new level 000B new password Command 4 8EH inverse password Secured Mode only ...

Page 503: ...Register SLC This register is the interface for the protection commands SLC Security Level Command RegisterESFR F0C0H 60H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMMAND rw Field Bits Type Description COMMAND 15 0 rw Security Level Control Command The commands to control the security level must be written to this register see table ...

Page 504: ...1 rh Security Level 1 00B Unprotected Mode default 01B Secured Mode 10B Reserved Do not use this combination 11B Write Protected Mode 1 While the security level is unprotected after reset it changes to write protected after the execution of instruction EINIT STATE 15 13 rh Current State of Switching State Machine 000B Awaiting command 0 or command 4 default 001B Awaiting command 1 010B Awaiting co...

Page 505: ...003H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 GLC CST OCD SEN 1 r rw rw r Field Bits Type Description 1 1 0 r Reserved Should be written with reset value 11B Will be changed in future versions OCDSEN 2 rw OCDS Cerberus Enable 0B OCDS and Cerberus are still in reset state 1B ODCS and Cerberus are operable GLCCST 3 rw Global CAPCOM Start This bit starts all CAPCOM units synchronously if enabled 0B CA...

Page 506: ... SCU User s Manual 6 246 V2 1 2008 08 SCU V1 13 6 15 2 Identification Block For identification of the most important silicon parameters a set of identification registers is defined that provide information on the chip manufacturer the chip type and its properties ...

Page 507: ...contains information about the manufacturer IDMANUF Manufacturer Identification Register ESFR F07EH 3FH Reset Value 1820H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MANUF DEPT r r Field Bits Type Description DEPT 4 0 r Department Indicates the department within Infineon 00HAIM MC MANUF 15 5 r Manufacturer This is the JEDEC normalized manufacturer code 0C1HInfineon Technologies AG ...

Page 508: ... Identification Register ESFR F07CH 3EH Reset Value XXXXH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHIPID Revision r r Field Bits Type Description Revision 7 0 r Device Revision Code Identifies the device step Please refer to the data sheet for the device specific value CHIPID 15 8 r Device Identification Identifies the device name Please refer to the data sheet for the device specific value ...

Page 509: ...Reset Value 3XXXH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TYPE SIZE r rw Field Bits Type Description SIZE 11 0 rw Size of on chip Program Memory The size of the implemented program memory in terms of 4 K blocks i e memory size SIZE 4 Kbyte Please refer to the data sheet for the device specific value TYPE 15 12 r Type of on chip Program Memory Identifies the memory type on this silicon Please refer t...

Page 510: ... 3 2 1 0 PROGVPP PROGVDD r r Field Bits Type Description PROGVDD 7 0 r Programming VDD Voltage The voltage of the standard power supply required to program or erase if applicable the on chip program memory Please refer to the data sheet for the device specific value PROGVPP 15 8 r Programming VPP Voltage The voltage of the special programming power supply if existent required to program or erase i...

Page 511: ...mory Registers The marker memory consists of following SFRs located in the DMP_M for free usage of the user software MKMEM0 Marker Memory 0 Register SFR FED0H 68H Reset Value 0000H MKMEM1 Marker Memory 1 Register SFR FED2H 69H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MARKER rw Field Bits Type Description MARKER 15 0 rw Marker Content ...

Page 512: ...gister F1AEH Sec Power on Reset DMP_M HPOSCCON High Precision Oscillator Configuration Register F1B4H Sec Power on Reset DMP_M PLLOSCCON PLL Control Register F1B6H Sec Power on Reset DMP_1 PLLSTAT PLL Status Register F0BCH Power on Reset DMP_1 STATCLR1 PLL Status Clear 1 Register F0E2H Sec Power on Reset DMP_1 PLLCON0 PLL Configuration 0 Register F1B8H Sec Power on Reset DMP_1 PLLCON1 PLL Configur...

Page 513: ...guration 0 Register F0B8H Sec Power on Reset DMP_M RSTCON1 Reset Configuration 1 Register F0BAH Sec Power on Reset DMP_M RSTCNTCON Reset Counter Configuration Register F1B2H Sec Power on Reset DMP_M SWRSTCON SW Reset Control Register F0AEH Sec Power on Reset DMP_M ESREXCON1 ESR 1 External Control Register FF32H Sec Power on Reset DMP_M ESREXCON2 ESR 2 External Control Register FF34H Sec Power on R...

Page 514: ...p 5 Sequence A F01EH Sec Power on Reset DMP_M PVC1CONA6 PVC_1 Register for Step 6 Sequence A F020H Sec Power on Reset DMP_M PVC1CONB1 PVC_1 Register for Step 1 Sequence B F024H Sec Power on Reset DMP_M PVC1CONB2 PVC_1 Register for Step 2 Sequence B F026H Sec Power on Reset DMP_M PVC1CONB3 PVC_1 Register for Step 3 Sequence B F028H Sec Power on Reset DMP_M PVC1CONB4 PVC_1 Register for Step 4 Sequen...

Page 515: ...P_M PVCMCONB3 PVC_M Register for Step 3 Sequence B F1F8H Sec Power on Reset DMP_M PVCMCONB4 PVC_M Register for Step 4 Sequence B F1FAH Sec Power on Reset DMP_M PVCMCONB5 PVC_M Register for Step 5 Sequence B F1FCH Sec Power on Reset DMP_M PVCMCONB6 PVC_M Register for Step 6 Sequence B F1FEH Sec Power on Reset DMP_M EVR1CON0 EVR_1 Control 0 Register F088H Sec Power on Reset DMP_M EVR1SET10V EVR_1 Se...

Page 516: ... Set A Register FEEAH Sec Power on Reset DMP_M SEQASTEP4 Sequence Step 4 for Set A Register FEECH Sec Power on Reset DMP_M SEQASTEP5 Sequence Step 5 for Set A Register FEEEH Sec Power on Reset DMP_M SEQASTEP6 Sequence Step 6 for Set A Register FEF0H Sec Power on Reset DMP_M SEQBSTEP1 Sequence Step 1 for Set B Register FEF4H Sec Power on Reset DMP_M SEQBSTEP2 Sequence Step 2 for Set B Register FEF6...

Page 517: ...CON1 External Interrupt Input Trigger Control 1 Register F032H Sec Application Reset DMP_1 EXICON2 External Interrupt Input Trigger Control 2 Register F034H Sec Application Reset DMP_1 EXICON3 External Interrupt Input Trigger Control 3 Register F036H Sec Application Reset DMP_1 EXOCON0 External Output Trigger Control 0 Register FE30H Sec Application Reset DMP_1 EXOCON1 External Output Trigger Cont...

Page 518: ...nd Trap Clear Register FE98H Sec Power on Reset DMP_M ISSR Interrupt Source Select Register FF2EH Sec Application Reset DMP_1 TCCR Temperature Compensation Control Register F1ACH Sec Application Reset DMP_1 TCLR Temperature Compensation Level Register F0ACH Sec Application Reset DMP_1 WDTREL WDT Reload Register F0C8H Sec Application Reset DMP_1 WDTCS WDT Control and Status Register F0C6H Sec Appli...

Page 519: ...ion Register F07EH Power on Reset DMP_1 IDCHIP Chip Identification Register F07CH Power on Reset DMP_1 IDMEM Program Memory Identification Register F07AH Power on Reset DMP_1 IDPROG Programming Voltage Identification Register F078H Power on Reset DMP_1 MKMEM0 Marker Memory 0 Register FED0H Sec Power on Reset DMP_M MKMEM1 Marker Memory 1 Register FED2H Sec Power on Reset DMP_M 1 Register write prot...

Page 520: ...U V1 13 6 17 Implementation This section shows the connections of the module to the system 6 17 1 Clock Generation Unit The following table shows the input connection of the Clock Genation Unit Table 6 24 CGU Input Connection Input Connected to XTAL 1 XTAL 1 XTAL 2 XTAL 2 CLKIN1 Port 2 9 CLKIN2 Port 4 4 ...

Page 521: ...y with the ESRx inputs listed in Table 6 25 and Table 6 26 is possibile Even if an ESRx pin is not avaliable an overlay with the ESRx inputs listed in the tables is possible The ESRx logic part is fully functional Table 6 25 ESR1 Input Connection Input Connected to Input 0 Port 2 4 Input 1 Port 3 0 Input 2 Port 10 0 Input 3 Port 1 0 Input 4 Port 1 2 Input 5 Port 2 1 Table 6 26 ESR2 Input Connectio...

Page 522: ...XC2200 Derivatives System Units Vol 1 of 2 System Control Unit SCU User s Manual 6 262 V2 1 2008 08 SCU V1 13 ...

Page 523: ... the maximum set of ports Table 7 1 Ports of the XC2200 Group Width I O Connected Modules P0 8 I O EBC A7 A0 CCU6 USIC CAN P1 8 I O EBC A15 A8 CCU6 P2 13 I O EBC READY BHE A23 A16 AD15 AD13 D15 D13 CAN CCU2 GPT12E USIC JTAG P3 8 I O EBC arbitration BREQ HLDA HOLD CAN USIC P4 8 I O EBC CS4 CS0 CCU2 CAN GPT12E P5 16 I Analog Inputs CCU6 JTAG GPT12E CAN P6 4 I O ADC GPT12E P7 5 I O P7 0 J LINK CAN GP...

Page 524: ...for one for analog inputs Each port pin contains one of them Figure 7 1 Structure of the Ports without Hardware Override Functionality Note INV signal is derived from Pn_IOCR PC 3 2 pin ALT1 Pn_IOCR ALT2 ALT3 TC 1 0 PD 2 0 1 1 1 pull devices 4 control 2 2 Standard_port_structure_4 vsd Access to port registers by PD Bus Alternate Data signals or other control lines from Peripherals or SCU output st...

Page 525: ... Save Mode as all other ports When HW_EN is active then the user should set the POCON PPSx 0 ENABQ pin ALT1 Pn_OUT Pn_IN Pn_OMR Pn_IOCR ALT2 1 1 1 1 pull devices 2 4 control 2 2 Access to port registers by PD Bus Alternate Data signals or other control lines from Peripherals input stage output stage ALTIN pad 4 ALTSEL0 1 TC 1 0 PD 2 0 DQ1 ENDQ1 1 3 1 2 ALT3 1 HW_OUT 1 HW_DIR 2 OD DIR msb Standard_...

Page 526: ...08 08 Parallel Ports V1 6D6 Figure 7 3 Structure of Port 5 and Port 15 Note There is always a standard digital input connected in parallel to each analog input pin Analog_port_digital_structure_2 vsd Access to port registers by PD Bus pad Pn_IN Input stage Pn_DIDIS Analog Input ENABQ ...

Page 527: ...he Pn_IOCR register Software can set or clear the bit Pn_OUT Px which drives the port pin in case it is selected by the output multiplexer An output driver with hardware override can select an additional output signal coming from a peripheral While the hardware override is activated this signal has higher priority than all other output signals and can not be deselected by the port In this case the...

Page 528: ... the driver strength can be adapted to the application requirements by bit fields PDMx The selection is done in groups of four pins The Port Output Control registers POCON provide the corresponding control bits A 4 bit control field configures the driver strength and the edge shape Word ports consume four control nibbles each byte ports consume two control nibbles each where each control nibble co...

Page 529: ... Driver strength 1 Edge Shape2 000 Strong driver Sharp edge mode 001 Strong driver Medium edge mode 010 Strong driver Soft edge mode 011 Weak driver 100 Medium driver 101 Medium driver 110 Medium driver 111 Weak driver 1 Defines the current the respective driver can deliver to the external circuitry 2 Defines the switching characteristics to the respective new output level This also influences the...

Page 530: ...l Register Controlled Pins by Px_POCON y z 1 1 x denotes the port number while y z represents the bit field range Port Width 15 12 11 8 7 4 3 0 P0_POCON P0 7 4 P0 3 0 8 P1_POCON P1 7 4 P1 3 0 8 P2_POCON CLOCKOUT driver2 at P2 8 2 The high speed clock driver at P2 8 is enabled instead of the standard driver while P2_POCON PDM3 xx1B The standard driver for P2 8 is added to the next lower pin group a...

Page 531: ...A2H 2 n Reset Value 0000H Pn_OUT n 6 11 Port n Output Register SFR FFA2H 2 n Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description Px x 0 15 x rwh Port Output Bit x This bit defines the level at the output pin of port Pn pin x if the output is selected...

Page 532: ...PS 11 PS 10 PS 9 PS 8 w w w w w w w w w w w w w w w w Field Bits Type Description PSx x 8 15 x 8 w Port Set Bit x Setting this bit sets or toggles the corresponding bit in the port output register Pn_OUT see Table 7 3 On a read access this bit returns X PCx x 8 15 x w Port Clear Bit x Setting this bit clears or toggles the corresponding bit in the port output register Pn_OUT see Table 7 3 On a rea...

Page 533: ...t Bit x Setting this bit sets or toggles the corresponding bit in the port output register Pn_OUT see Table 7 3 On a read access this bit returns X PCx x 0 7 x 8 w Port Clear Bit x Setting this bit clears or toggles the corresponding bit in the port output register Pn_OUT see Table 7 3 On a read access this bit returns X Table 7 3 Function of the Bits PCx and PSx PCx PSx Function 0 or no write acc...

Page 534: ...gister SFR FF80H 2 n Reset Value 0000H 1 P15_IN Port 15 Input Register SFR FF9EH Reset Value 0000H 1 1 Px bits for non implemented I O lines are always read as 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description Px x 0 15 x rh Port Input Bit x This bit indicates the level at the in...

Page 535: ...utput Control Register x XSFR E800H 2 x Reset Value 0000H P1_IOCRx x 00 07 Port 1 Input Output Control Register x XSFR E820H 2 x Reset Value 0000H P2_IOCRx x 00 12 Port 2 Input Output Control Register x XSFR E840H 2 x Reset Value 0000H P3_IOCRx x 00 07 Port 3 Input Output Control Register x XSFR E860H 2 x Reset Value 0000H P4_IOCRx x 00 07 Port 4 Input Output Control Register x XSFR E880H 2 x Rese...

Page 536: ...erved Table 7 4 PC Coding PC 3 0 I O Selected Pull up down Selected Output Function Behavior in Power Saving Mode1 0000B Direct Input No pull device connected Input value Pn_OUT x no pull 0001B Pull down device connected Input value 0 pull down 0010B Pull up device connected Input value 1 pull up 0011B No pull device connected Bit Pn_OUT x reflects the current input value Input value Pn_OUT x no p...

Page 537: ...urpose Output 1101B Output function ALT1 1110B Output function ALT2 1111B Output function ALT3 1 In power saving mode the input Schmitt trigger is always switched off A defined input value is driven to the internal circuitry instead of the level detected at the input pin 2 If the IOCR setting is inverted input then an inverted signal Pn_OUT is driven internally The Pn_OUT register itself always co...

Page 538: ...egister P5_DIDIS is a 16 bit register and P15_DIDIS is an 8 bit register P5_DIDIS Port 5 Digital Input Disable RegisterSFR FE8AH Reset Value 0000H P15_DIDIS Port 15 Digital Input Disable RegisterSFR FE9EH Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bit Type Description Py y 0 15 ...

Page 539: ...s in the port registers always start right aligned For example a port comprising only 8 pins only uses the bit positions 7 0 of the corresponding register The remaining bit positions are filled with 0 r The pad driver mode registers may be different for each port As a result they are described independently for each port in the corresponding chapter ...

Page 540: ...tput Modification Register Low E9C0H XXXXH P0_POCON Port 0 Output Control Register E8A0H 0000H P0_IOCR00 Port 0 Input Output Control Register 0 E800H 0000H P0_IOCR01 Port 0 Input Output Control Register 1 E802H 0000H P0_IOCR02 Port 0 Input Output Control Register 2 E804H 0000H P0_IOCR03 Port 0 Input Output Control Register 3 E806H 0000H P0_IOCR04 Port 0 Input Output Control Register 4 E808H 0000H ...

Page 541: ...tput Modification Register Low E9C4H XXXXH P1_POCON Port 1 Output Control Register E8A2H 0000H P1_IOCR00 Port 1 Input Output Control Register 0 E820H 0000H P1_IOCR01 Port 1 Input Output Control Register 1 E822H 0000H P1_IOCR02 Port 1 Input Output Control Register 2 E824H 0000H P1_IOCR03 Port 1 Input Output Control Register 3 E826H 0000H P1_IOCR04 Port 1 Input Output Control Register 4 E828H 0000H ...

Page 542: ...AH XXXXH P2_POCON Port 2 Output Control Register E8A4H 0000H P2_IOCR00 Port 2 Input Output Control Register 0 E840H 0000H P2_IOCR01 Port 2 Input Output Control Register 1 E842H 0000H P2_IOCR02 Port 2 Input Output Control Register 2 E844H 0000H P2_IOCR03 Port 2 Input Output Control Register 3 E846H 0000H P2_IOCR04 Port 2 Input Output Control Register 4 E848H 0000H P2_IOCR05 Port 2 Input Output Cont...

Page 543: ...r while bitfield P2_POCON PDM3 xx1B Bit P2_POCON PPS3 has no function The standard driver of pin P2 8 is controlled by bits P2_POCON PDM2 and PPS2 along with pins P2 7 P2 4 The standard driver is the default selection Register P2_IOCR08 controls the driver that is currently active P2_IOCR10 Port 2 Input Output Control Register 10 E854H 0000H P2_IOCR11 Port 2 Input Output Control Register 11 E856H ...

Page 544: ...tput Modification Register Low E9CCH XXXXH P3_POCON Port 3 Output Control Register E8A6H 0000H P3_IOCR00 Port 3 Input Output Control Register 0 E860H 0000H P3_IOCR01 Port 3 Input Output Control Register 1 E862H 0000H P3_IOCR02 Port 3 Input Output Control Register 2 E864H 0000H P3_IOCR03 Port 3 Input Output Control Register 3 E866H 0000H P3_IOCR04 Port 3 Input Output Control Register 4 E868H 0000H ...

Page 545: ...tput Modification Register Low E9D0H XXXXH P4_POCON Port 4 Output Control Register E8A8H 0000H P4_IOCR00 Port 4 Input Output Control Register 0 E880H 0000H P4_IOCR01 Port 4 Input Output Control Register 1 E882H 0000H P4_IOCR02 Port 4 Input Output Control Register 2 E884H 0000H P4_IOCR03 Port 4 Input Output Control Register 3 E886H 0000H P4_IOCR04 Port 4 Input Output Control Register 4 E888H 0000H ...

Page 546: ...chmitt trigger in the input stage must be disabled This is achieved by setting the corresponding bit in the register P5_DIDIS Figure 7 9 Port 5 Register Overview Table 7 10 Port 5 Registers Register Short Name Register Long Name Address Offset Reset Value P5_IN Port 5 Input Register FF8AH 0000H P5_DIDIS Port 5 Digital Input Disable Register FE8AH 0000H Port5_Regs vsd P5_DIDIS Data Registers P5_IN ...

Page 547: ...dress Offset Reset Value P6_OUT Port 6 Output Register FFAEH 0000H P6_IN Port 6 Input Register FF8CH 0000H P6_OMRL Port 6 Output Modification Register Low E9D8H XXXXH P6_POCON Port 6 Output Control Register E8ACH 0000H P6_IOCR00 Port 6 Input Output Control Register 0 E8C0H 0000H P6_IOCR01 Port 6 Input Output Control Register 1 E8C2H 0000H P6_IOCR02 Port 6 Input Output Control Register 2 E8C4H 0000...

Page 548: ...UT Port 7 Output Register FFB0H 0000H P7_IN Port 7 Input Register FF8EH 0000H P7_OMRL Port 7 Output Modification Register Low E9DCH XXXXH P7_POCON Port 7 Output Control Register E8AEH 0000H P7_IOCR00 Port 7 Input Output Control Register 0 E8E0H 0000H P7_IOCR01 Port 7 Input Output Control Register 1 E8E2H 0000H P7_IOCR02 Port 7 Input Output Control Register 2 E8E4H 0000H P7_IOCR03 Port 7 Input Outp...

Page 549: ...er FF90H 0000H P8_OMRL Port 8 Output Modification Register Low E9E0H XXXXH P8_POCON Port 8 Output Control Register E8B0H 0000H P8_IOCR00 Port 8 Input Output Control Register 0 E900H 0000H P8_IOCR01 Port 8 Input Output Control Register 1 E902H 0000H P8_IOCR02 Port 8 Input Output Control Register 2 E904H 0000H P8_IOCR03 Port 8 Input Output Control Register 3 E906H 0000H P8_IOCR04 Port 8 Input Output...

Page 550: ... 9 Output Modification Register Low E9E4H XXXXH P9_POCON Port 9 Output Control Register E8B2H 0000H P9_IOCR00 Port 9 Input Output Control Register 0 E920H 0000H P9_IOCR01 Port 9 Input Output Control Register 1 E922H 0000H P9_IOCR02 Port 9 Input Output Control Register 2 E924H 0000H P9_IOCR03 Port 9 Input Output Control Register 3 E926H 0000H P9_IOCR04 Port 9 Input Output Control Register 4 E928H 0...

Page 551: ...H P10_POCON Port 10 Output Control Register E8B4H 0000H P10_IOCR00 Port 10 Input Output Control Register 0 E940H 0000H P10_IOCR01 Port 10 Input Output Control Register 1 E942H 0000H P10_IOCR02 Port 10 Input Output Control Register 2 E944H 0000H P10_IOCR03 Port 10 Input Output Control Register 3 E946H 0000H P10_IOCR04 Port 10 Input Output Control Register 4 E948H 0000H P10_IOCR05 Port 10 Input Outp...

Page 552: ...ut Output Control Register 11 E956H 0000H P10_IOCR12 Port 10 Input Output Control Register 12 E958H 0000H P10_IOCR13 Port 10 Input Output Control Register 13 E95AH 0000H P10_IOCR14 Port 10 Input Output Control Register 14 E95CH 0000H P10_IOCR15 Port 10 Input Output Control Register 15 E95EH 0000H Table 7 15 Port 10 Registers cont d Register Short Name Register Long Name Address Offset Reset Value ...

Page 553: ..._IN Port 11 Input Register FF96H 0000H P11_OMRL Port 11 Output Modification Register Low E9ECH XXXXH P11_POCON Port 11 Output Control Register E8B6H 0000H P11_IOCR00 Port 11 Input Output Control Register 0 E960H 0000H P11_IOCR01 Port 11 Input Output Control Register 1 E962H 0000H P11_IOCR02 Port 11 Input Output Control Register 2 E964H 0000H P11_IOCR03 Port 11 Input Output Control Register 3 E966H...

Page 554: ...tt trigger in the input stage must be disabled This is achieved by setting the corresponding bit in the register P15_DIDIS Figure 7 16 Port 15 Register Overview Table 7 17 Port 15 Registers Register Short Name Register Long Name Address Offset Reset Value P15_IN Port 15 Input Register FF9EH 0000H P15_DIDIS Port 15 Digital Input Disable Register FE9EH 0000H Port15_Regs vsd P15_DIDIS Data Registers ...

Page 555: ...example EBC Table 7 18 summarizes the various function of each pin of the XC2200 Notes to Pin Definitions 1 Ctrl The output signal for a port pin is selected via bitfield PC in the associated register Px_IOCRy Output O0 is selected by setting the respective bitfield PC to 1x00B output O1 is selected by 1x01B etc Output signal OH is controlled by hardware 2 Type Indicates the employed pad type St s...

Page 556: ...Output CCU60_COU T60 O1 St B CCU60 Channel 0 Output TDI_D I St B JTAG Test Data Input 8 P7 0 O0 I St B Bit 0 of Port 7 General Purpose Input Output T3OUT O1 St B GPT1 Timer T3 Toggle Latch Output T6OUT O2 St B GPT2 Timer T6 Toggle Latch Output TDO OH St B JTAG Test Data Output ESR2_1 I St B ESR2 Trigger Input 1 RxDC4B I St B CAN Node 4 Receive Data Input 9 P7 3 O0 I St B Bit 3 of Port 7 General Pu...

Page 557: ...el 1 Shift Clock Input 13 P8 1 O0 I St B Bit 1 of Port 8 General Purpose Input Output CCU60_CC6 1 O1 I St B CCU60 Channel 1 Input Output 14 P8 0 O0 I St B Bit 0 of Port 8 General Purpose Input Output CCU60_CC6 0 O1 I St B CCU60 Channel 0 Input Output 16 P6 0 O0 I St A Bit 0 of Port 6 General Purpose Input Output EMUX0 O1 St A External Analog MUX Control Output 0 ADC0 BRKOUT O3 St A OCDS Break Sign...

Page 558: ...I In A Analog Input Channel 0 for ADC1 22 P15 1 I In A Bit 1 of Port 15 General Purpose Input ADC1_CH1 I In A Analog Input Channel 1 for ADC1 23 P15 2 I In A Bit 2 of Port 15 General Purpose Input ADC1_CH2 I In A Analog Input Channel 2 for ADC1 T5IN I In A GPT2 Timer T5 Count Gate Input 24 P15 3 I In A Bit 3 of Port 15 General Purpose Input ADC1_CH3 I In A Analog Input Channel 3 for ADC1 T5EUD I I...

Page 559: ...DI_A I In A JTAG Test Data Input 35 P5 3 I In A Bit 3 of Port 5 General Purpose Input ADC0_CH3 I In A Analog Input Channel 3 for ADC0 T3IN I In A GPT1 Timer T3 Count Gate Input 39 P5 4 I In A Bit 4 of Port 5 General Purpose Input ADC0_CH4 I In A Analog Input Channel 4 for ADC0 CCU63_T12 HRB I In A External Run Control Input for T12 of CCU63 T3EUD I In A GPT1 Timer T3 External Up Down Control Input...

Page 560: ...t 11 of Port 5 General Purpose Input ADC0_CH11 I In A Analog Input Channel 11 for ADC0 47 P5 12 I In A Bit 12 of Port 5 General Purpose Input ADC0_CH12 I In A Analog Input Channel 12 for ADC0 48 P5 13 I In A Bit 13 of Port 5 General Purpose Input ADC0_CH13 I In A Analog Input Channel 13 for ADC0 EX0BINB I In A External Interrupt Trigger Input 49 P5 14 I In A Bit 14 of Port 5 General Purpose Input ...

Page 561: ...ta Line 13 RxDC0C I St B CAN Node 0 Receive Data Input 56 P2 1 O0 I St B Bit 1 of Port 2 General Purpose Input Output TxDC0 O1 St B CAN Node 0 Transmit Data Output CCU63_CC6 1 O2 I St B CCU63 Channel 1 Input Output AD14 OH I St B External Bus Interface Address Data Line 14 ESR1_5 I St B ESR1 Trigger Input 5 EX0AINA I St B External Interrupt Trigger Input 57 P11 4 O0 I St B Bit 4 of Port 11 General...

Page 562: ...available in step AA RxDC0A I St B CAN Node 0 Receive Data Input 62 P11 2 O0 I St B Bit 2 of Port 11 General Purpose Input Output CCU63_CCP OS2A I St B CCU63 Position Input 2 63 P4 1 O0 I St B Bit 1 of Port 4 General Purpose Input Output TxDC2 O2 St B CAN Node 2 Transmit Data Output CC2_25 O3 I St B CAPCOM2 CC25IO Capture Inp Compare Out CS1 OH St B External Bus Interface Chip Select 1 Output 64 P...

Page 563: ...urpose Input Output TxDC2 O2 St B CAN Node 2 Transmit Data Output CC2_26 O3 I St B CAPCOM2 CC26IO Capture Inp Compare Out CS2 OH St B External Bus Interface Chip Select 2 Output T2IN I St B GPT1 Timer T2 Count Gate Input 69 P2 6 O0 I St B Bit 6 of Port 2 General Purpose Input Output U0C0_SELO 0 O1 St B USIC0 Channel 0 Select Control 0 Output U0C1_SELO 1 O2 St B USIC0 Channel 1 Select Control 1 Out...

Page 564: ...ne 0 U1C0_DX0A I St B USIC1 Channel 0 Shift Data Input 76 P4 5 O0 I St B Bit 5 of Port 4 General Purpose Input Output CC2_29 O3 I St B CAPCOM2 CC29IO Capture Inp Compare Out 77 P4 6 O0 I St B Bit 6 of Port 4 General Purpose Input Output CC2_30 O3 I St B CAPCOM2 CC30IO Capture Inp Compare Out T4IN I St B GPT1 Timer T4 Count Gate Input 78 P2 7 O0 I St B Bit 7 of Port 2 General Purpose Input Output U...

Page 565: ...t EXTCLK O2 DP B Programmable Clock Signal Output 1 CC2_21 O3 I DP B CAPCOM2 CC21IO Capture Inp Compare Out A21 OH DP B External Bus Interface Address Line 21 U0C1_DX1D I DP B USIC0 Channel 1 Shift Clock Input 81 P4 7 O0 I St B Bit 7 of Port 4 General Purpose Input Output CC2_31 O3 I St B CAPCOM2 CC31IO Capture Inp Compare Out T4EUD I St B GPT1 Timer T4 External Up Down Control Input 82 P2 9 O0 I ...

Page 566: ...St B ESR1 Trigger Input 2 U0C0_DX0A I St B USIC0 Channel 0 Shift Data Input U0C1_DX0A I St B USIC0 Channel 1 Shift Data Input 85 P3 0 O0 I St B Bit 0 of Port 3 General Purpose Input Output U2C0_DOUT O1 St B USIC2 Channel 0 Shift Data Output BREQ OH St B External Bus Request Output ESR1_1 I St B ESR1 Trigger Input 1 U2C0_DX0A I St B USIC2 Channel 0 Shift Data Input RxDC3B I St B CAN Node 3 Receive ...

Page 567: ...ternal Bus Hold Acknowledge Output Input Output in master mode input in slave mode U2C0_DX0B I St B USIC2 Channel 0 Shift Data Input 89 P10 2 O0 I St B Bit 2 of Port 10 General Purpose Input Output U0C0_SCLK OUT O1 St B USIC0 Channel 0 Shift Clock Output CCU60_CC6 2 O2 I St B CCU60 Channel 2 Input Output AD2 OH I St B External Bus Interface Address Data Line 2 U0C0_DX1B I St B USIC0 Channel 0 Shif...

Page 568: ...quest Input 94 P2 10 O0 I St B Bit 10 of Port 2 General Purpose Input Output U0C1_DOUT O1 St B USIC0 Channel 1 Shift Data Output U0C0_SELO 3 O2 St B USIC0 Channel 0 Select Control 3 Output CC2_23 O3 I St B CAPCOM2 CC23IO Capture Inp Compare Out A23 OH St B External Bus Interface Address Line 23 U0C1_DX0E I St B USIC0 Channel 1 Shift Data Input CAPIN I St B GPT2 Register CAPREL Capture Input 95 P10...

Page 569: ...97 P3 3 O0 I St B Bit 3 of Port 3 General Purpose Input Output U2C0_SELO 0 O1 St B USIC2 Channel 0 Select Control 0 Output U2C1_SELO 1 O2 St B USIC2 Channel 1 Select Control 1 Output U2C0_DX2A I St B USIC2 Channel 0 Shift Control Input RxDC3A I St B CAN Node 3 Receive Data Input 98 P10 4 O0 I St B Bit 4 of Port 10 General Purpose Input Output U0C0_SELO 3 O1 St B USIC0 Channel 0 Select Control 3 Ou...

Page 570: ...put 100 P10 5 O0 I St B Bit 5 of Port 10 General Purpose Input Output U0C1_SCLK OUT O1 St B USIC0 Channel 1 Shift Clock Output CCU60_COU T62 O2 St B CCU60 Channel 2 Output AD5 OH I St B External Bus Interface Address Data Line 5 U0C1_DX1B I St B USIC0 Channel 1 Shift Clock Input 101 P3 5 O0 I St B Bit 5 of Port 3 General Purpose Input Output U2C1_SCLK OUT O1 St B USIC2 Channel 1 Shift Clock Output...

Page 571: ...t Output U0C0_DOUT O1 St B USIC0 Channel 0 Shift Data Output TxDC4 O2 St B CAN Node 4 Transmit Data Output U1C0_SELO 0 O3 St B USIC1 Channel 0 Select Control 0 Output AD6 OH I St B External Bus Interface Address Data Line 6 U0C0_DX0C I St B USIC0 Channel 0 Shift Data Input U1C0_DX2D I St B USIC1 Channel 0 Shift Control Input CCU60_CTR APA I St B CCU60 Emergency Trap Input 104 P3 6 O0 I St B Bit 6 ...

Page 572: ...7 O0 I St B Bit 7 of Port 0 General Purpose Input Output U1C1_DOUT O1 St B USIC1 Channel 1 Shift Data Output U1C0_SELO 3 O2 St B USIC1 Channel 0 Select Control 3 Output A7 OH St B External Bus Interface Address Line 7 U1C1_DX0B I St B USIC1 Channel 1 Shift Data Input CCU61_CTR APB I St B CCU61 Emergency Trap Input 107 P3 7 O0 I St B Bit 7 of Port 3 General Purpose Input Output U2C1_DOUT O1 St B US...

Page 573: ...P9 0 O0 I St B Bit 0 of Port 9 General Purpose Input Output CCU63_CC6 0 O1 I St B CCU63 Channel 0 Input Output 113 P10 8 O0 I St B Bit 8 of Port 10 General Purpose Input Output U0C0_MCLK OUT O1 St B USIC0 Channel 0 Master Clock Output U0C1_SELO 0 O2 St B USIC0 Channel 1 Select Control 0 Output AD8 OH I St B External Bus Interface Address Data Line 8 CCU60_CCP OS1A I St B CCU60 Position Input 1 U0C...

Page 574: ...1C0_SELO 5 O2 St B USIC1 Channel 0 Select Control 5 Output U2C1_DOUT O3 St B USIC2 Channel 1 Shift Data Output A9 OH St B External Bus Interface Address Line 9 ESR2_3 I St B ESR2 Trigger Input 3 EX1BINA I St B External Interrupt Trigger Input U2C1_DX0C I St B USIC2 Channel 1 Shift Data Input 117 P10 10 O0 I St B Bit 10 of Port 10 General Purpose Input Output U0C0_SELO 0 O1 St B USIC0 Channel 0 Sel...

Page 575: ...62 Channel 2 Input Output U1C0_SELO 6 O2 St B USIC1 Channel 0 Select Control 6 Output U2C1_SCLK OUT O3 St B USIC2 Channel 1 Shift Clock Output A10 OH St B External Bus Interface Address Line 10 ESR1_4 I St B ESR1 Trigger Input 4 CCU61_T12 HRB I St B External Run Control Input for T12 of CCU61 EX2AINA I St B External Interrupt Trigger Input U2C1_DX0D I St B USIC2 Channel 1 Shift Data Input U2C1_DX1...

Page 576: ...access when WR active for ext writes to the low byte when WRL U1C0_DX0D I St B USIC1 Channel 0 Shift Data Input 124 P1 3 O0 I St B Bit 3 of Port 1 General Purpose Input Output CCU62_COU T63 O1 St B CCU62 Channel 3 Output U1C0_SELO 7 O2 St B USIC1 Channel 0 Select Control 7 Output U2C0_SELO 4 O3 St B USIC2 Channel 0 Select Control 4 Output A11 OH St B External Bus Interface Address Line 11 ESR2_4 I...

Page 577: ...1_DX0C I St B USIC0 Channel 1 Shift Data Input RxDC3C I St B CAN Node 3 Receive Data Input 129 P1 4 O0 I St B Bit 4 of Port 1 General Purpose Input Output CCU62_COU T61 O1 St B CCU62 Channel 1 Output U1C1_SELO 4 O2 St B USIC1 Channel 1 Select Control 4 Output U2C0_SELO 5 O3 St B USIC2 Channel 0 Select Control 5 Output A12 OH St B External Bus Interface Address Line 12 U2C0_DX2B I St B USIC2 Channe...

Page 578: ... T62 O2 St B CCU63 Channel 2 Output CCU63 _CTRAPA I St B CCU63 Emergency Trap Input CCU60_CCP OS1B I St B CCU60 Position Input 1 133 P1 6 O0 I St B Bit 6 of Port 1 General Purpose Input Output CCU62_CC6 1 O1 I St B CCU62 Channel 1 Input Output U1C1_SELO 2 O2 St B USIC1 Channel 1 Select Control 2 Output U2C0_DOUT O3 St B USIC2 Channel 0 Shift Data Output A14 OH St B External Bus Interface Address L...

Page 579: ...2 unconnected Voltages on XTAL1 must comply to the core supply voltage VDDI1 138 PORST I In B Power On Reset Input A low level at this pin resets the XC2200 completely A spike filter suppresses input pulses 10 ns Input pulses 100 ns safely pass the filter The minimum duration for a safe recognition should be 120 ns An internal pullup device will hold this pin high when nothing is driving it 139 ES...

Page 580: ...ral Purpose Input Output CCU60_COU T63 O1 St B CCU60 Channel 3 Output CCU60_CTR APB I St B CCU60 Emergency Trap Input BRKIN_D I St B OCDS Break Signal Input 143 P8 5 O0 I St B Bit 5 of Port 8 General Purpose Input Output CCU60_COU T62 O1 St B CCU60 Channel 2 Output TCK_D I St B JTAG Clock Input 15 VDDIM PS M Digital Core Supply Voltage for Domain M Decouple with a ceramic capacitor see Data Sheet ...

Page 581: ...s and all ports except P5 P6 and P15 are fed from supply voltage VDDPB 1 37 73 109 VSS PS Digital Ground All VSS pins must be connected to the ground line or ground plane 1 To generate the reference clock output for bus timing measurement fSYS must be selected as source for EXTCLK and P2 8 must be selected as output pin Also the high speed clock pad must be enabled This configuration is referred t...

Page 582: ...terrupt or trap Class A or Class B requests via an external signal e g a power fail signal generate wake up request signals generate hardware reset requests ESR0 is bidirectional by default ESR1 and ESR2 can optionally output a reset signal data control input for CCU6x MultiCAN and USIC ESR1 or ESR2 software controlled input output signal Table 8 1 XC2200 Dedicated Pins Pin s Function PORST Power ...

Page 583: ...or debugging purposes the on chip debugging system can be enabled by driving pin TRST high at the rising edge of PORST The Control Pin for Core Voltage Generation TRef was used to control the generation method for the core supply voltage VDDI in step AA For that step pin TRef must be connected to VDDPB use the on chip EVRs This connection is no more required from step AB on For the current step pi...

Page 584: ...ied supply voltage range please refer to the corresponding Data Sheets These pins supply the output drivers as well as the on chip EVVRs VDDPB except for external core voltage supply The respective VDDP VSS pairs should be decoupled as close to the pins as possible The Ground Reference pins VSS provide the ground reference voltage for the power supplies as well as the reference voltage for the inp...

Page 585: ...ternal address space can be restricted by enabling only the required address lines Up to 5 external CS signals can be generated in order to save external glue logic Memories or peripherals with variable access time are supported via a particular Ready function A HOLD HLDA protocol is available for bus arbitration The XC2200 External Bus Controller EBC allows access to external peripherals memories...

Page 586: ...elated to the reference CLocK OUTput CLKOUT1 All bus signals are generated in relation to the rising edge of this clock The external bus protocol is compatible with those of the C166 Family and the XC166 Family These improvements are configured via an enhanced register set see above in comparison to C166 Family The C16x registers SYSCON and BUSCONx are no longer used But because the configuration ...

Page 587: ...able WRite High byte strobe active low BHE mode activated for every data access to the upper byte of the 16 bit bus handled as additional address bit WRH mode activated for high byte write accesses on a 16 bit bus READY READY I P2 READY used for dynamic wait state insertion programmable active high or low AD 12 0 AD 15 13 I O P10 P2 Address Data bus in multiplexed mode this bus is used for both ad...

Page 588: ... previous cycle tristate wait states after CS switch Phase A cycles are not inserted at every access cycle but only when changing the CS If an access using one CS CSx was finished and the next access with a different CS CSy is started then Phase A cycle s are performed according to the control bits as set in the first CS CSx The A Phase cycles are inserted while the addresses and ALE of the next c...

Page 589: ...h tristate wait states B phase Addresses valid ALE high no command ALE length C phase Addresses valid ALE low no command R W delay D phase Write data valid ALE low no command Data valid for write cycles E phase Command read or write active Access time F phase Command inactive address hold Read data tristate time write data hold time MCT05374 A B C D E F Valid Valid 0 3 1 2 0 3 0 1 1 32 0 3 Phases ...

Page 590: ...sses valid ALE high no command ALE length C phase addresses valid ALE low no command Address hold R W delay D phase address tristate for read cycles data valid for write cycles ALE low no command E phase command read or write active Access time F phase command inactive address hold Read data tristate time write data hold time Address Valid MCT05376 A B C D E F Valid Data In 0 3 1 2 0 3 0 1 1 32 0 ...

Page 591: ...e if there are three tristate cycles programmed and two idle cycles occur then the A phase takes only one clock 9 2 2 2 B Phase Address Setup ALE Phase The B phase can take 1 2 clocks It is used for addressing devices before giving a command and defines the length of time that ALE is active In multiplexed bus mode the address is applied for latching 9 2 2 3 C Phase Delay Phase The C phase is simil...

Page 592: ...ks Addresses and write data are held while the command is inactive The number of wait states inserted during the F phase is independently programmable for read and write accesses The F phase is used to program tristate wait states on the bidirectional data bus in order to avoid bus conflicts for read accesses and to assure data hold times for write accesses The F phase is configured individually f...

Page 593: ...pends also on the pad timing Therefore the number of required cycles for a bus access depends on the current system frequency The minimum bus cycles shown below cannot be achieved at very high system frequencies Figure 9 6 Fastest Read Cycle Demultiplexed Bus Figure 9 7 Fastest Write Cycle Demultiplexed Bus MCT05378 b CLK e ALE Valid ADDR CS RD Valid DATA In MCT05379 b CLK e ALE Valid ADDR CS WR V...

Page 594: ...0 V2 1 2008 08 EBC_X8 V1 0d1 Figure 9 8 Fastest Read Cycle Multiplexed Bus Figure 9 9 Fastest Write Cycle Multiplexed Bus MCT05380 b CLK d ALE Valid ADDR CS RD Data Valid Muxed Address Out Data In e f Addr Valid MCT05381 b CLK e ALE Valid ADDR CS RD Valid Muxed Address Out Data Out Addr Valid ...

Page 595: ... one CS MultiCAN and USIC related registers are used to control the access to the internal LXBus CS0 is the default chip select signal that is active whenever no other chip select or internal address space is addressed Therefore CS0 has no ADDRSEL register Note All EBC registers are write protected by the EINIT protection mechanism Thus after execution of the EINIT instruction these registers are ...

Page 596: ...ipherals MCA05382_XC EBCMOD0 EBCMOD1 TCONCS0 FCONCS0 TCONCS1 FCONCS1 ADDRSEL1 TCONCS2 FCONCS2 ADDRSEL2 TCONCS3 FCONCS3 ADDRSEL3 TCONCS7 FCONCS7 ADDRSEL7 00EE00 00EE02 00EE10 00EE12 00EE18 00EE1A 00EE1E 00EE20 00EE22 00EE26 00EE28 00EE2A 00EE2E 00EE48 00EE4A 00EE4E 00EE8E General EBC Control CS0 Channel Control CS1 Channel Control CS2 Channel Control CS3 Channel Control CS7 Channel Control TCONCS4 ...

Page 597: ... Timing Configuration Register 0000H FCONCS1 EE1AH CS1 Function Configuration Register 0000H ADDRSEL1 EE1EH CS1 Address Size and Range Register 0000H TCONCS2 EE20H CS2 Timing Configuration Register 0000H FCONCS2 EE22H CS2 Function Configuration Register 0000H ADDRSEL2 EE26H CS2 Address Size and Range Register 0000H TCONCS3 EE28H CS3 Timing Configuration Register 0000H FCONCS3 EE2AH CS3 Function Co...

Page 598: ...arity1 0B READY is active low 1B READY is active high RDYDIS 14 rw READY Pin Disable1 0B READY enabled 1B READY disabled ALEDIS 13 rw ALE Pin Disable 0B ALE enabled 1B ALE disabled BYTDIS 12 rw BHE Pin Disable 0B BHE enabled 1B BHE disabled WRCFG2 11 rw Configuration for Pins WR WRL BHE WRH 0B WR and BHE 1B WRL and WRH EBCDIS 10 rw EBC Pins Disable 0B EBC is using the pins for external bus 1B EBC ...

Page 599: ...to use the pins for arbitration and not for General Purpose IO GPIO If ARBEN is cleared the arbitration inputs HLDA and HOLD are fixed internally to an inactive high state Additionally the master slave setting of the arbiter is done with a separate bit SLAVE 4 The reset value depends on the selected startup configuration CSPEN 7 4 rw CSx Pins Enable only external CSx 0000BAll external Chip Select ...

Page 600: ...DIS rw rw rw rw rw Field Bits Type Description WRPDIS 7 rw WR WRL Pin Disable 0B WR WRL pin enabled 1B WR WRL pin disabled DHPDIS 6 rw Data High Port Pins Disable 0B Address Data bus pins 15 8 enabled 1B Address Data bus pins 15 8 disabled ALPDIS 5 rw Address Low Pins Disable 0B Address bus pins 7 0 generally enabled depending on APDIS A0PDIS 1B Address bus pins 7 0 disabled A0PDIS 4 rw Address Bi...

Page 601: ...t valid for the next access TCONCS0 Timing Cfg Reg for CS0 XSFR EE10H Reset Value 7C3DH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRPHF RDPHF PHE PHD PHC PHB PHA rw rw rw rw rw rw rw Field Bits Type Description WRPHF 14 13 rw Write Phase F 00B 0 clock cycles 11B 3 clock cycles default RDPHF 12 11 rw Read Phase F 00B 0 clock cycles default 11B 3 clock cycles PHE 10 6 rw Phase E 00000B1 clock cycle defa...

Page 602: ...7 6 5 4 3 2 1 0 WRPHF RDPHF PHE PHD PHC PHB PHA rw rw rw rw rw rw rw Field Bits Type Description WRPHF 14 13 rw Write Phase F 00B 0 clock cycles 11B 3 clock cycles RDPHF 12 11 rw Read Phase F 00B 0 clock cycles 11B 3 clock cycles PHE 10 6 rw Phase E 00000B1 clock cycle 11111B32 clock cycles PHD 5 rw Phase D 0B 0 clock cycles 1B 1 clock cycle PHC 4 3 rw Phase C 00B 0 clock cycles 11B 3 clock cycles...

Page 603: ... rw Phase A 00B 0 clock cycles 11B 3 clock cycles TCONCS7 Timing Cfg Reg for CS7 XSFR EE48H Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRPHF RDPHF PHE PHD PHC PHB PHA r r r r r r r Field Bits Type Description WRPHF 14 13 r Write Phase F 00B 0 clock cycles RDPHF 12 11 r Read Phase F 00B 0 clock cycles PHE 10 6 r Phase E 00000B1 clock cycle PHD 5 r Phase D 0B 0 clock cycles PHC 4 3 r Ph...

Page 604: ...et Value 0011H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BTYP RDY MOD RDY EN EN CS rw rw rw rw Field Bits Type Description BTYP 5 4 rw Bus Type Selection 00B 8 bit Demultiplexed 01B 08 bit Multiplexed 10B 16 bit Demultiplexed 11B 16 bit Multiplexed RDYMOD 2 rw Ready Mode 0B Asynchronous READY 1B Synchronous READY RDYEN 1 rw Ready Enable 0B Access time is controlled by bit field PHEx 1B Access time is ...

Page 605: ...without chip select signal FCONCSx x 1 4 Function Cfg Reg for CSx XSFR EE12H x 8 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BTYP RDY MOD RDY EN EN CS rw rw rw rw Field Bits Type Description BTYP 5 4 rw Bus Type Selection 00B 8 bit Demultiplexed 01B 8 bit Multiplexed 10B 16 bit Demultiplexed 11B 16 bit Multiplexed RDYMOD 2 rw Ready Mode 0B Asynchronous READY 1B Synchronous READY RDYEN ...

Page 606: ...ss to the LXBus peripherals MultiCAN and USIC FCONCS7 Function Cfg Reg for CS7 XSFR EE4AH Reset Value 0027H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BTYP RDY MOD RDY EN EN CS r r r r Field Bits Type Description BTYP 5 4 r Bus Type Selection 10B 16 bit Demultiplexed RDYMOD 2 r Ready Mode 1B Synchronous READY RDYEN 1 r Ready Enable 1B Access time is controlled by bit field PHEx and READY signal ENCS 0 ...

Page 607: ...finition of Address Areas The enabled register sets FCONCSx TCONCSx ADDRSELx x 1 4 7 define separate address areas within the address space of the XC2200 Within each of these address areas the conditions of external accesses and LXBus accesses x 7 can be ADDRSELx x 1 4 Address Range Size for CSx XSFR EE16H x 8 Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw Field Bits Type...

Page 608: ...a from C0 0000H to FF FFFFH 4 Mbytes is used by the internal program memory Therefore these address areas cannot be used by external resources connected to the external bus Note The range start address can only be on boundaries specified by the selected range size according to Table 9 4 Table 9 4 Address Range and Size for ADDRSELx ADDRSELx Address Window Range Size RGSZ Relevant R Bits of RGSAD S...

Page 609: ...xternal area using the corresponding set of control registers FCONCSx TCONCSx and ignoring registers ADDRSELy An overlapping of windows of this group will lead to an undefined behaviour Priority 2 A match with registers ADDRSELy y 1 3 7 directs the access to the respective external area using the corresponding set of control registers FCONCSy TCONCSy An overlapping of windows of this group will le...

Page 610: ... actual end of the current bus cycle The external device drives READY active in order to indicate that data has been latched write cycle or is available read cycle The READY pin is generally enabled by setting the bit RDYDIS in EBCMOD0 to 0 in order to switch the corresponding port pin Also the polarity of the READY is defined inside the EBCMOD0 register on the RDYPOL bit For a specific address wi...

Page 611: ...ait state or READY control logic takes a while to generate the READY signal when a cycle was started After a predefined number of clock cycles the EBC will start checking its READY line to determine the end of the bus cycle When using the READY function with so called normally ready peripherals it may lead to erroneous bus cycles if the READY line is sampled too early These peripherals pull their ...

Page 612: ...n as arbitration master or as arbitration slave by programming bit SLAVE in register EBCMOD0 The selected mode and the arbitration gets active by the first setting of bit HLDEN in CPU register PSW Afterwards a change of the slave master mode is not possible without resetting the device Of course for arbitration the dedicated pins have to be activated by setting bit EBCMOD0 ARBEN 9 3 8 2 Arbitratio...

Page 613: ...the Arbitration Master Note Figure 9 13 shows the first possibility for BREQ to get active The XC2200 will complete the currently running bus cycle before granting the external bus as indicated by the broken lines MCT05385 Not fixed number of cycles 0 n HOLD HLDA BREQ CSx WRH WR WRL RD ADD DATA BHE Earliest Change Not Active Driven Pull Up High Impedance ...

Page 614: ...2200 requesting the bus 9 3 8 3 Arbitration Slave Scheme If the EBC is configured as arbitration slave it is by default not owner of the external bus and has to request the bus first As long as it has not finished all its queued requests and the arbitration master is not requesting the bus the arbitration slave stays owner of the bus For the description of the signal handling of the handshake see ...

Page 615: ...ster and the other as slave and both are working on the same external bus as bus master they can be connected directly together for bus arbitration as shown in Figure 9 15 As both EBCs assume after reset to own the external bus the slave CPU has to be released from reset and initialized first before starting the master CPU The other way is to start both systems at the same time but then both EBC m...

Page 616: ...cycles see Table 9 5 Only when this shutdown sequence is terminated the shutdown acknowledge is generated from EBC and from other modules as described for SCU and the chip can enter the requested mode Table 9 5 gives an overview of the shutdown control in EBC depending on the EBC configuration Table 9 5 EBC Shutdown Control Arbitration Mode Master Mode Slave Mode Bus Control With Control of the Bu...

Page 617: ...CONCS7 will be lengthened with waitstate s controlled by the MultiCAN USIC itself with the READY function This timing control is defined by the TCONCS7 value of 0000H Accesses to the LXBus do not generate valid external bus cycles on an enabled external bus interface the configured chip select signals are driven high the external control signal pins RD WR ALE are driven inactive and then switched ...

Page 618: ...tivates a startup configuration during reset may be simple pull resistors for systems that use this feature upon every reset You may want to use a switchable solution via jumpers or an external signal for systems that only temporarily use a hardware configuration 2 By executing the following software sequence using SCU_SWRSTCON and SCU_RSTCON1 registers a Write respective configuration value refer...

Page 619: ...arding the way they are affected by start up procedure 1 registers initialized after any start up 2 registers initialized after start up triggered by a power on in DMP_1 power domain Note Power on in DMP_M domain means power on also in DMP_1 The registers in Table 10 2 are grouped in accordance to the above differentiation Table 10 1 XC2200 Start Up Mode Configuration Start Up Mode STSTAT HWCFG Va...

Page 620: ...input for PLL PLLCON2 0000H K1 divider 1 PLLCON3 8007H K2 divider 8 SYSCON0 0002H The PLL output fPLL used as system clock WUOSCCON 0000H Wake up Oscillator enabled with fWU approx 500kHz HPOSCCON U u0uu UUH PLLSTAT FINDIS bit will not be set in an OSCWDT emergency case PLLOSCCON XXXXH Device specific value chip to chip trimming EVRMCON0 0110H EVR_M Control 0 register EVR1CON0 0D10H EVR_1 Control ...

Page 621: ...ation on such special cases and their handling refer to XC2000 Programmer s Guide 10 2 2 System Frequency The system clock which is active when the first user instruction is executed depends on the currently selected start up mode and the last start up trigger after power on in all modes except CAN Bootstrap Loader Chapter 10 6 4 10MHz nominal value from the XC2200 internal oscillator doubled freq...

Page 622: ...ocedure Is STMEM0 WDTCSOE bit set AND Is the start up caused by a WDT reset If both the above conditions are true a Watchdog Timer Double Error is recognized and Start up Error state is immediately entered by the device Therefore if entering power save mode upon WDT Double Error is not desired for some reasons the user software must care to reset STMEM0 WDTCSOE bit Different possibilities for hand...

Page 623: ...M power supply domain and is Security protected The following start up information can be exchanged with application software using this register 1 the user software can influence the next device start up by writing into STMEM0 bits 15 13 11 The supported feature SRAM initialization is described in Chapter 10 3 3 2 the emergency status flags indicated in SCU_SYSCON0 bits 15 12 upon device start up...

Page 624: ... Source Status 1 EMSPWR 2 rw PVC1 Emergency Event Source Status 1 SELSTAT 3 rw Clock Select Status 1 WDTCSOE 4 rw Watchdog Timer Overflow Error status flag 2 2 Bit copied from WDTCS OE upon startup 0 10 5 r Reserved do not change these bits RINPS 11 rw Initialization of the PSRAM 0 not requested 1 will be performed upon start up RINDS 12 rw Initialization of the DSRAM 0 not requested 1 will be per...

Page 625: ...EM0 register will be anyway reset 10 3 3 Preparing to activate Parity XC2200 supports parity as memory content protection mechanism which can request trap or reset upon a single bit data error refer to Memory Content Protection Section 6 13 The user software must activate parity trap reset generation for any one of PSRAM DSRAM and DPRAM only after every location from the respective memory is writt...

Page 626: ...s requested in STMEM0 13 11 if STMEM0 15 1 after startup meaning RAMs have been just initialized RAM initialization request is cleared STMEM0 15 11 00000B parity is configured enabled as required by the application if STMEM0 15 0 after functional reset not power on RAM initialization is not needed and the request is not active parity is configured as required by the application this is needed beca...

Page 627: ... PSRAM Enable parity as needed P11_MR RAM_Init_Request v2 vsd Power on RAM Initialization is needed Trigger an Application Software Reset SCU_RSTCON0 0300H Execute SRST instruction Clear RAM Initialization Request SCU_STMEM0 SCU_STMEM0 07FFH Application Software EINIT Register protection activated Application specific system initialization Parity will be used No Yes Power On or Functional reset SC...

Page 628: ...t mode is expected to be the configuration used in most cases this mode can be selected by pulling high just 2 pins 10 5 External Start When external start mode is configured the XC2200 begins executing code out of an off chip memory first instruction from location 00 0000H connected to the XC2200 s external bus interface The External Bus Controller is adjusted to the employed external memory by e...

Page 629: ...5 16 Bit Data DeMUX BHE mode A0 1 0 0 P0 0 P0 7 P1 0 P1 7 P2 0 P2 2 P2 11 P10 0 P10 14 16 Bit Data DeMUX WRH mode A0 1 0 1 P0 0 P0 7 P1 0 P1 7 P2 0 P2 2 P2 11 P10 0 P10 14 16 Bit Data DeMUX BHE mode A1 1 1 0 P2 0 P2 2 P10 0 P10 15 16 Bit Data DeMUX WRH mode A1 1 1 1 P0 0 P0 7 P1 0 P1 7 P2 0 P2 2 P10 0 P10 7 P10 13 P10 14 Table 10 4 EBC Configuration Address Width Available Address Lines Cfg Pins P...

Page 630: ...l start mode Specific State in EBC Registers Configuration at P10 10 8 EBCMOD0 15 8 EBCMOD1 FCONCSx 1 1 Which FCONCSx registers are affected is dependant on the configuration at P10 14 13 as follows 11B or 01B FCONCS0 is affected 10B FCONCS0 and FCONCS1 are affected 00B FCONCS0 FCONCS4 are affected The other unaffected FCONCS registers retain their default values refer to Section 9 3 5 Comment EBC...

Page 631: ...mory or internal Flash required for the initialization code The BSL mechanism may be used for standard system startup as well as only for special occasions like system maintenance firmware update or end of line programming or testing The XC2200 supports bootstrap loading using several protocols modes Standard UART protocol loading 32 bytes see Section 10 6 2 1 UART protocol Enhanced bootstrap load...

Page 632: ...al memory This process may go through several iterations or may directly execute the final application Note Data fetches from a protected Flash will not be executed Exiting Bootstrap Loader Mode The watchdog timer and the debug system are disabled as long as the Bootstrap loader is active Watchdog timer and debug system are released automatically when the BSL terminates after having received the l...

Page 633: ...e external host to the XC2200 using asynchronous eight bit data frames without parity 1 start bit 1 stop bit The number of data bytes to be received in standard UART boot mode is fixed to 32 bytes which allows up to 16 two byte instructions Figure 10 2 Bootstrap Loader Sequence The XC2200 scans the RxD line to receive a zero byte after entering UART BSL mode and the respective initialization The z...

Page 634: ...ly use the pre initialized interface U0C0 to receive data and store it to arbitrary user defined locations The example code below shows how to fit such a 2nd level loader into the available 32 bytes This is possible due to the pre initialized serial channel and the pre set registers see Table 10 8 Example for Secondary UART Bootstrap Loader Routine TargetStart LIT 0E00020H Definition of target are...

Page 635: ... for USIC0 Channel 0 U0C0_PCRL 0401H 1 stop bit three RxD samples at point 4 U0C0_SCTRL 0002H Passive data level 1 U0C0_SCTRH 0707H 8 data bits U0C0_FDRL 43FFH Normal divider mode 1 1 selected U0C0_BRGH 0XXXH Measured PDIV value zero byte in bits 9 0 U0C0_BRGL 1C00H Normal mode FDIV 8 clocks bit U0C0_DX0CR 0003H Data input selection DPP1 0081H Points to USIC0 base address 1 1 This register setting...

Page 636: ...interface U0C0 accordingly and switches pin TxD to output Using this baudrate an identification byte DAH is returned to the host The next steps in this mode are to process the so called Bootloader Header as follows 1 XC2200 sends the current PDIV divider from U0C0_BRGH register the 10 bit value is sent in 2 bytes Note In this bootloader the multi byte values are sent in high to low order 2 XC2200 ...

Page 637: ...ller family supporting Enhanced UART BSL mode the code defined for it is DAH Note The identification byte does not directly identify a specific derivative This information can in this case be obtained from the identification registers Table 10 9 Enhanced UART BSL Specific State Item Value Comments U0C0_CCR 0002H ASC mode selected for USIC0 Channel 0 U0C0_PCRL 0401H 1 stop bit three RxD samples at ...

Page 638: ... baudrate For a correct data transfer from the host to the XC2200 the maximum deviation between the internal initialized baudrate for U0C0 and the real baudrate of the host should be below 2 5 The deviation FB in percent between host baudrate and XC2200 baudrate can be calculated via Equation 10 1 10 1 Note Function FB does not consider the tolerances of oscillators and other devices supporting th...

Page 639: ...o which communication with the external host will work properly without additional tests or investigations Higher baudrates however may be used as long as the actual deviation does not exceed the indicated limit A certain baudrate marked I in Figure 10 3 may e g violate the deviation limit while an even higher baudrate marked II in Figure 10 3 stays very well below it Any baudrate can be used for ...

Page 640: ...ived in SSC boot mode is user selectable The serial clock rate is set to fSYS 10 which results in 1 MHz after a power reset Once SSC BSL mode is entered and the respective initialization done the XC2200 first reads the header from the first addresses 00 0 of the target EEPROM This header consists of two items The memory identification byte D5H The data size field 1 byte or 2 bytes depending on the...

Page 641: ...ytes indicated as XXH depends on the employed EEPROM type Table 10 10 Determining the EEPROM Type SSC Frame Number Meaning of Transmitted Data Received Data from 8 bit Addr Device Received Data from 16 bit Addr Device 1 03H Read command XXH default level XXH default level 2 00H Address byte high for 16 bit addr XXH default level XXH default level 3 00H Address byte low D5H Identification byte XXH ...

Page 642: ...0_PCRL 0011H SSC master mode frequency from fPPP U0C0_PCRH 8000H MCLK generation is enabled U0C0_SCTRL 0103H MSB first passive data level 1 U0C0_SCTRH 073FH 8 data bits infinite frame U0C0_DX0CR 0015H Data input selection U0C0_FDRL 43FFH Normal divider mode 1 1 selected U0C0_BRGL 0000H Normal mode FDIV default value after reset U0C0_BRGH 8004H Passive levels MCLK SCLK 0 PDIV 4 P2_IOCR03 00D0H P2 3...

Page 643: ...o determine the CAN baud rate at which the external host is communicating Therefore the external host must send initialization frames continuously to the XC2200 The first two data bytes of the initialization frame must include a 2 byte baud rate detection pattern 5555H an 11 bit sent in 2 bytes identifier ACKID1 for the acknowledge frame a 16 bit data message count value DMSGC and an 11 bit 2 byte...

Page 644: ... data frame the bootstrap loader finishes and executes the loaded code Timing Parameters There are no general restrictions for CAN timings of the external host During the initialization phase the external host transmits initialization frames If no acknowledge frame is sent back within a certain time as defined in the external host e g after a dedicated number of initialization frame transmissions ...

Page 645: ...esses Table 10 13 CAN BSL Specific State Item Value Comments P2_IOCR05 00A0H P2 5 is push pull output TxD P2_IOCR06 0020H P2 6 is input with pull up RxD SCU_HPOSCCON 0030H OSC_HP enabled External Crystal Clock mode SCU_SYSCON0 0001H OSC_HP selected as system clock CAN_MOCTR0L 0008H Message Object 0 Control low CAN_MOCTR0H 00A0H Message Object 0 Control high CAN_MOCTR1L 0000H Message Object 1 Contr...

Page 646: ...ferred Data Supported Host Speed Standard UART x110B RxD P7 4 100 144 pin TxD P7 3 100 144 pin 32 bytes 2 4 19 2 kbaud RxD P2 4 64 pin TxD P2 3 64 pin Enhanced UART x010B RxD P7 4 100 144 pin TxD P7 3 100 144 pin l bytes 2 2 l Code_Length sent by the host the values allowed are 1 PSRAM_size 256 2 4 19 2 kbaud at start then changeable by Header RxD P2 4 64 pin TxD P2 3 64 pin Sync Serial 1001B MRST...

Page 647: ...ace supports very low latency triggers between XC2200 and tool and or system environment if needed The memory mapped OCDS registers are accessible via the JTAG interface using Cerberus In addition there is a limited set of special Cerberus debug IO instructions As an alternative the OCDS can be controlled by a debug monitor program which communicates with the tool over a user interface like CAN Th...

Page 648: ... interface for OCDS JTAG port based on the IEEE 1149 1 2001 JTAG standard Break interface for external trigger input and signaling of internal triggers Generic memory access functionality Independent data transfer channel for e g programming of flash memory The Debug Interface is represented by Standard JTAG Interface with 4 pins Two optional trigger pins OCDS Break Interface Note The JTAG clock f...

Page 649: ...on which needs as many IO pins as possible In the XC2200 these signals are only provided as alternate functions no dedicated pins To minimize the impact caused by the debug interface pins these signals can be mapped to several pins Thus each application can select the variant with the least impact This is controlled via the Debug Pin Routing Register DBGPRR Pin BRKOUT can be assigned to pins P6 0 ...

Page 650: ... TDI 00 P5 2 01 P10 10 10 P7 2 11 P8 3 DPRTMS 5 4 rw Debug Pin Routing for TMS 00 P5 4 01 P10 11 10 P7 3 11 P8 4 DPRTCK 7 6 rw Debug Pin Routing for TCK 00 P2 9 01 P10 9 10 P7 4 11 P8 5 DPRBRKIN 9 8 rw Debug Pin Routing for BRKIN 00 P5 10 01 P10 8 10 P7 1 11 P8 6 TRSTL 15 rh TRST Pin Start up Value This bit indicates if the Debug Mode can be entered or not 0 A debugger can not be connected 1 A deb...

Page 651: ...sked comparisons for hardware breakpoints The OCDS can also be configured by a monitor Support of multi CPU master system Single stepping with monitor or CPU halt PC is visible in halt mode IO_READ_IP instruction injection via Cerberus Basic Concept The on chip debug concept is split up into two parts The first part covers the generation of debug events and the second part defines what actions are...

Page 652: ...nals are matching with the programmed conditions The following hardware trigger sources can be used Table 11 1 Hardware Triggers Trigger Source Size Task Identifier 16 bits Instruction Pointer 24 bits Data address of reads two busses monitored 2 24 bits Data address of writes 24 bits Data value reads or writes 16 bits Debug Event Sources Debug Actions MCB05389 Debug Event Processing SBRK Instructi...

Page 653: ...struction has been decoded and it reaches the Execute stage the whole pipeline is canceled including the SBRK itself Hence in fact the SBRK instruction is never executed by itself The further behavior is dependent on how OCDS has been programmed if the OCDS is enabled and the software breakpoints are also enabled then the CPU goes into Halt Mode if the OCDS is disabled or the software breakpoints ...

Page 654: ...d by higher priority user interrupts It then relies on the external debugger system to interrogate the target purely through reading and updating via the debug interface Call a Monitor One of the possible actions to be taken when a debug event is raised is to call a Monitor Program This short entry to a Monitor allows a flexible debug environment to be defined which is capable of satisfying many o...

Page 655: ...ter for internal bus locking situations The target application of Cerberus is to use the JTAG interface as an independent port for On Chip Debug Support The external debugger can access the OCDS registers and arbitrary memory locations with the injection mechanism 11 3 1 Functional Overview Cerberus is operated by an external debugger across the JTAG Interface The Debugger supplies Cerberus IO Ins...

Page 656: ...g on the CPU The data transfers are made via a PDBus register The external host is master of all transactions requesting the monitor to write or read a value The difference to Read Write Mode of Operation is that the read or write request now is not actively executed by the Cerberus but it sets request bits in a CPU accessible register to signal the Monitor that the host wants to send IO_WRITE_WOR...

Page 657: ...e JTAG module using standard JTAG instructions IEEE1149 1 Note For Boundary Scan to operate properly the JTAG interface must use the default pins The reset value of register DBGPRR ensures this Initialization of Boundary Scan The following sequence is defined to activate Boundary Scan mode Set PORST 1 TRST 1 TESTM 1 Negative Pulse on PORST Wait for Power Domain to startup Negative pulse on TRST to...

Page 658: ...asses Grouping the various instruction into classes aids in identifying similar instructions e g SHR ROR and variations of certain instructions e g ADD ADDB This provides an easy access to the possibilities and the power of the instructions of the XC2200 Note The used mnemonics refer to the detailed description Table 12 1 Arithmetic Instructions Addition of two words or bytes ADD ADDB Addition wit...

Page 659: ...ld in either the high or the low byte of a word BFLDH BFLDL Setting a single bit to 1 BSET Clearing a single bit to 0 BCLR Movement of a single bit BMOV Movement of a negated bit BMOVN ANDing of two bits BAND ORing of two bits BOR XORing of two bits BXOR Comparison of two bits BCMP Table 12 5 Shift and Rotate Instructions Shifting right of a word SHR Shifting left of a word SHL Rotating right of a...

Page 660: ...stack POP Saving of a word on the system stack and then updating the old word with a new value provided for register bank switching SCXT Table 12 9 Jump Instructions Conditional jumping to an either absolutely indirectly or relatively addressed target instruction within the current code segment JMPA JMPI JMPR Unconditional jumping to an absolutely addressed target instruction within any code segme...

Page 661: ...hin any code segment CALLS Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack PCALL Unconditional branching to the interrupt or trap vector jump table in code segment VECSEG TRAP Table 12 11 Return Instructions Returning from a subroutine within the current code segment RET Returning ...

Page 662: ...a NOP instruction PWRDN Servicing the Watchdog Timer SRVWDT Disabling the Watchdog Timer DISWDT Enabling the Watchdog Timer can only be executed in WDT enhanced mode ENWDT Signifying the end of the initialization routine switches the register security mechanism to protected and disables the effect of any later execution of a DISWDT instruction in WDT compatibility mode EINIT Table 12 13 Miscellane...

Page 663: ...nvolved registers Decoding all 32 bits of a protected doubleword instruction increases the security in cases of data distortion during instruction fetching Critical operations like a software reset are therefore only executed if the complete instruction is decoded without an error This enhances the safety and reliability of a microcontroller system Table 12 14 MAC Unit Instructions Multiply and Ac...

Page 664: ...e not contained in this manual but rather provided in a separate Data Sheet which can be updated more frequently Please refer to the current version of the Data Sheet of the respective device for all electrical parameters Note In any case the specific characteristics of a device should be verified before a new design is started This ensures that the used information is up to date The XC2200 deriva...

Page 665: ... 15 P1 4 P10 14 V D DI1 P9 5 P9 4 P1 3 P10 13 P9 3 P10 12 P1 2 P9 2 P10 11 P10 10 P1 1 P10 9 P9 1 P10 8 P9 0 P1 0 V DDPB V SS P2 1 V SS V D DPB P5 4 P5 5 P5 6 P5 7 P5 8 P5 9 P5 10 P5 11 P5 12 P5 13 P5 14 P5 15 P2 12 P2 11 P11 5 V DDI1 P2 0 P11 4 P2 2 P11 3 P4 0 P2 3 P11 2 P4 1 P2 4 P11 1 P11 0 P2 5 P4 2 P2 6 P4 4 P4 3 V DDPB LQFP 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 9...

Page 666: ...84 83 82 81 80 79 78 77 76 V DDPB ESR0 ESR1 PORST XTAL1 XTAL2 P1 7 P1 6 P1 5 P10 15 P1 4 P10 14 V DDI1 P1 3 P10 13 P10 12 P1 2 P10 11 P10 10 P1 1 P10 9 P10 8 P1 0 V DDPB V S S 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 P2 4 46 47 48 49 50 V SS V DDPB P5 8 P5 9 P5 10 P5 11 P5 13 P5 15 P2 12 P2 11 V DDI1 P2 0 P2 1 P2 2 P4 0 P2 3 P4 1 P2 5 P4 2 P2 6 P4 3 V DDPB 75 74 73 72 71 70 69 6...

Page 667: ...upts 20 12 2 Message acceptance filtering 20 21 2 Message object FIFO 20 36 2 Message object lists 20 13 2 Node control 20 9 2 Overview 20 4 2 Registers LISTiH 20 57 2 LISTiL 20 58 2 MCR 20 55 2 MITR 20 56 2 MOAMRnH 20 95 2 MOAMRnL 20 95 2 MOARnH 20 97 2 MOARnL 20 98 2 MOCTRnH 20 79 2 20 82 2 MOCTRnL 20 80 2 20 82 2 MODATAnHH 20 101 2 MODATAnHL 20 101 2 MODATAnLH 20 100 2 MODATAnLL 20 100 2 MOFCRn...

Page 668: ...tor run detection 6 12 1 Clock system Clock source 6 6 1 PLL see PLL Concatenation of Timers 14 22 2 14 47 2 Context Pointer Updating 4 34 1 Switch 4 33 1 Switching 5 34 1 Count direction 14 6 2 14 36 2 Counter 14 20 2 14 45 2 Counter Mode GPT1 14 10 2 14 40 2 CPU 2 2 1 4 1 1 D Data Management Unit Introduction 2 9 1 Data Page 4 42 1 Development Support 1 8 1 Direction count 14 6 2 14 36 2 Disable...

Page 669: ...ystem 2 8 1 5 2 1 L Latency Interrupt PEC 5 40 1 LXBus 2 14 1 M Memory 2 10 1 Multiplication 4 62 1 O OCDS Requests 5 39 1 P PEC 2 10 1 5 20 1 Latency 5 40 1 Transfer Count 5 21 1 Peripheral Event Controller PEC 5 20 1 Summary 2 15 1 Pins 8 1 1 Pipeline 4 11 1 PLL 6 5 1 Functionality 6 6 1 Switching parameters 6 14 1 Port 2 30 1 Temperature compensation 6 206 1 Ports Configuring a Pin 7 14 1 Outpu...

Page 670: ... interrupts 19 120 2 Protocol registers 19 123 2 Pulse shaping 19 118 2 Receive buffer 19 122 2 Signals 19 111 2 Sync break detection 19 122 2 Baud rate 19 8 2 Channel structure 19 5 2 Data buffer 19 10 2 Data shifting and handling 19 9 2 Data transfer interrupts 19 22 2 External frequency 19 42 2 Feature set 19 2 2 FIFO buffer 19 11 2 FIFO data buffer 19 80 2 Fractional divider 19 42 2 General in...

Page 671: ...G 19 29 2 CCR 19 26 2 Channel control and configuration registers 19 26 2 Data buffer registers 19 70 2 DX0CR 19 39 2 DX1CR 19 39 2 DX2CR 19 39 2 FDRH 19 48 2 FDRL 19 47 2 FIFO buffer and bypass registers 19 90 2 FMRH 19 69 2 FMRL 19 68 2 INPRH 19 33 2 INPRL 19 32 2 Input stage register 19 39 2 INx 19 106 2 KSCFG 19 30 2 OUTDRH 19 108 2 OUTDRL 19 108 2 OUTRH 19 107 2 OUTRL 19 107 2 Overview 19 14 ...

Page 672: ...ers overview 19 14 2 SSC mode 19 131 2 Automatic Shadow mechanism 19 139 2 Baud rate 19 142 2 Data frame control 19 140 2 EOF control 19 147 2 19 150 2 Master mode 19 142 2 Protocol interrupts 19 146 2 19 149 2 Protocol registers 19 151 2 Receive buffer 19 141 2 Signals 19 131 2 Slave mode 19 149 2 Slave select delay 19 145 2 Slave select generation 19 143 2 Time quanta counter 19 45 2 Transmit bu...

Page 673: ..._LISTiH 20 57 2 CAN_LISTiL 20 58 2 CAN_MCR 20 55 2 CAN_MITR 20 56 2 CAN_MOAMRnH 20 95 2 CAN_MOAMRnL 20 95 2 CAN_MOARnH 20 97 2 CAN_MOARnL 20 98 2 CAN_MOCTRnH 20 79 2 CAN_MOCTRnL 20 80 2 CAN_MODATAnHH 20 101 2 CAN_MODATAnHL 20 101 2 CAN_MODATAnLH 20 100 2 CAN_MODATAnLL 20 100 2 CAN_MOFCRnH 20 89 2 CAN_MOFCRnL 20 91 2 CAN_MOFGPRnH 20 93 2 CAN_MOFGPRnL 20 93 2 CAN_MOIPRnH 20 87 2 CAN_MOIPRnL 20 87 2 ...

Page 674: ...6x_IEN 18 97 2 CCU6x_INP 18 100 2 CCU6x_IS 18 90 2 CCU6x_ISR 18 95 2 CCU6x_ISS 18 93 2 CCU6x_KSCFG 18 110 2 CCU6x_KSCSR 18 112 2 CCU6x_MCMCTR 18 83 2 CCU6x_MCMOUT 18 86 2 CCU6x_MCMOUTS 18 85 2 CCU6x_MODCTR 18 77 2 CCU6x_PISELH 18 108 2 CCU6x_PISELL 18 106 2 CCU6x_PSLR 18 82 2 CCU6x_T12 18 32 2 CCU6x_T12DTC 18 35 2 CCU6x_T12MSEL 18 40 2 CCU6x_T12PR 18 32 2 CCU6x_T13 18 62 2 CCU6x_T13PR 18 63 2 CCU6...

Page 675: ...5 21 1 PECISNC 5 29 1 PECSEGx 5 25 1 Pn_DIDIS P15 7 16 1 P5 7 16 1 Pn_IN 7 12 1 Pn_IOCRx 7 13 1 Pn_OMRH P10 7 10 1 P2 7 10 1 Pn_OMRL 7 10 1 Pn_OUT 7 9 1 Pn_POCON 7 7 1 Ports Pn_IN 7 12 1 Pn_IOCRx 7 13 1 Pn_OMR 7 10 1 PROCONx 3 63 1 PSW 4 56 1 Q QR0 1 4 45 1 QX0 1 4 47 1 R RELH L 15 10 2 RTC_CON 15 6 2 RTC_IC 15 14 2 RTC_ISNC 15 14 2 RTC_KSCCFG 15 15 2 RTC_RELH L 15 10 2 RTC_RTCH L 15 9 2 RTC_T14 1...

Page 676: ... 47 2 UxCy_FMRH 19 69 2 UxCy_FMRL 19 68 2 UxCy_INPRH 19 33 2 UxCy_INPRL 19 32 2 UxCy_INx 19 106 2 UxCy_KSCFG 19 30 2 UxCy_OUTDRH 19 108 2 UxCy_OUTDRL 19 108 2 UxCy_OUTRH 19 107 2 UxCy_OUTRL 19 107 2 UxCy_PCRH 19 34 2 19 126 2 19 153 2 19 178 2 19 200 2 UxCy_PCRL 19 34 2 19 123 2 19 151 2 19 178 2 19 198 2 UxCy_PSCR 19 36 2 UxCy_PSR 19 35 2 19 127 2 19 155 2 19 181 2 19 201 2 UxCy_RBCTRH 19 103 2 U...

Page 677: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG B158 H9132 G1 X 7600 ...

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