Infineon Technologies XC2200, User Manual

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XC2200 Derivatives
System Units (Vol. 1 of 2)
Central Processing Unit (CPU)
User’s Manual 4-34 V2.1, 2008-08
CPUSV2_X, V2.2
Switching the Context of the Global Register Bank
The contents of the global register bank are switched by changing the base address of
the memory-mapped GPR bank. The base address is given by the contents of the
Context Pointer (CP).
After the CP has been updated, a state machine starts to store the old contents of the
global register bank and to load the new one. The store and load algorithm is executed
in nineteen CPU cycles: the execution of the cache validation process takes sixteen
cycles plus three cycles to stall an instruction execution to avoid pipeline conflicts upon
the completion of the validation process. The context switch process has two phases:
•
Store phase: The contents of the global register bank
1)
is stored back into the
DPRAM by executing eight injected STORE instructions. After the last STORE
instruction the contents of the global register bank are invalidated.
• Load phase: The global register bank is loaded with the new context by executing
eight injected LOAD instructions. After the last LOAD instruction the contents of the
global register bank are validated.
The code execution is stopped until the global register bank is valid again. A hardware
interrupt can occur during the validation process. The way the validation process is
completed depends on the type of register bank selected for this interrupt:
•
If the interrupt also uses a global register bank the validation process is finished
before executing the service routine (see
Figure 4-9 ).
• If the interrupt uses a local register bank the validation process is interrupted and the
service routine is executed immediately (see
Figure 4-10 ). After switching back to
the global register bank, the validation process is finished:
– If the interrupt occurred during the store phase, the entire validation process is
restarted from the very beginning.
– If the interrupt occurred during the load phase, only the load phase is repeated.
If a local-bank interrupt routine (Task B in Figure 4-11 ) is again interrupted by a global-
bank interrupt (Task C), the suspended validation process must be finished before code
of Task C can be executed. This means that the validation process of Task A does not
affect the interrupt latency of Task B but the latency of Task C.
Note: If Task C would immediately interrupt Task A, the register bank validation process
of Task A would be finished first. The worst case interrupt latency is identical in
both cases (see
Figure 4-9 and Figure 4-11 ).
1) During the store phase of the context switch the complete register bank is written to the DPRAM even if the
application only uses a part of this register bank. A register bank must not be located above FDE0
H
, otherwise
the store phase will overwrite SFRs (beginning at FE00
H
).