178
November, 2018 Rev.1.4
15.4 Register Description
15.4.1 FLASH Control Registers Description
FMR (FLASH Mode Register)
E1
H
7
6
5
4
3
2
1
0
AEF
PBUFF
FSEL
ESEL
OTPE
VFY
READ
nFERST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 01
H
AEF
FLASH Bulk Erase Enable.
0
FLASH Bulk Erase Disabled
1
FLASH Bulk Erase Enabled
PBUFF
Select Flash Page Buffer.
0
Main cell selected.
1
Page buffer selected.
OTPE
Select OTP area
0
No operation
1
OTP READ/WRITE is enabled
VFY
Enable verify mode with PGM or ERASE bit
0
No verify operation
1
Program Verify with PGM=1
Erase Verify with ERASE=1
READ
FLASH Read(VFY=0) or Write(program or erase) Verify(VFY=1). This bit
initiates reading the entire FLASH area, and must be set in chip test
mode, debugger mode or rom writing mode. Clear all FARH, FARM and
FARL before setting this bit for proper operation.
0
No operation
1
Start Read or Verify operation
nFERST
Reset FLASH/EEPROM Controller. This bit is auto-set after 1 system
clock period.
0
No operation
1
Reset internal registers for FLASH/EEPROM Controller
Caution
: The FEMR register is not used in normal operation including self programming. Do not alter
the contents of this register if possible.
FARH (FLASH Address Register High)
E9
H
7
6
5
4
3
2
1
0
-
-
-
-
FADDR19
FADDR17
FADDR17
FADDR16
-
-
-
-
R/W
R/W
R/W
R/W
Initial value : 00
H
FADDR[19:16]
Flash Address High (Write)
Checksum result in auto verify mode (Read)
FARM (FLASH Address Register Middle)
EA
H
7
6
5
4
3
2
1
0
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
