Abov MC96FR364B, User Manual

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54 November, 2018 Rev.1.4
10.4 Interrupt Vectors
There are 16 interrupt sources which are from internal peripherals or from external pin inputs. When a
interrupt is requested while EA bit in IE register and its individual enable bit INTnE in IEx register is
set, the CPU executes a long call instruction (LCALL) to the vector address listed in Table 10-2. As
can be seen in the table, all interrupt vector has 8 bytes address space except for reset vector. If
priority level is not set by user software, the interrupt sources have default priority as in the following
table, and the lower number has the higher priority.
Interrupt Source Symbol
Interrupt
Enable Bit
Priority Mask
Vector
Address
Hardware Reset RESETB Always 0 Non-Maskable 0000
H
- INT0 IE0.0 1 Maskable 0003
H
External Interrupt 0
INT1 IE0.1 2 Maskable 000B
H
External Interrupt 1
INT2 IE0.2 3 Maskable 0013
H
External Interrupt 2 INT3 IE0.3 4 Maskable 001B
H
External Interrupt 3 INT4 IE0.4 5 Maskable 0023
H
Pin Change Interrupt (P0)
INT5 IE0.5 6 Maskable 002B
H
- INT6 IE1.0 7 Maskable 0033
H
IRI INT7 IE1.1 8 Maskable 003B
H
BOD Flag
INT8 IE1.2 9 Maskable 0043
H
USART RX0
INT9 IE1.3 10 Maskable 004B
H
USART TX0 INT10 IE1.4 11 Maskable 0053
H
USART RX1 INT11 IE1.5 12 Maskable 005B
H
USART TX1
INT12 IE2.0 13 Maskable 0063
H
T0 INT13 IE2.1 14 Maskable 006B
H
T1 INT14 IE2.2 15 Maskable 0073
H
T2
INT15 IE2.3 16 Maskable 007B
H
T3
INT16 IE2.4 17 Maskable 0083
H
I2C INT17 IE2.5 18 Maskable 008B
H
REMOCON INT18 IE3.0 19 Maskable 0093
H
KEYSCAN
INT19 IE3.1 20 Maskable 009B
H
WT INT20 IE3.2 21 Maskable 00A3
H
WDT INT21 IE3.3 22 Maskable 00AB
H
BIT
INT22 IE3.4 23 Maskable 00B3
H
FLASH
INT23 IE3.5 24 Maskable 00BB
H
Table 10-2 Reset and Interrupt Vectors Placement
To activate a interrupt request, both EA bit in IE register and INTnE bit in IEx register are enabled.
When a interrupt is generated, the interrupt flag can be read through each status register except for
KEYSCAN and Pin Change Interrupt which have no status register. And almost interrupt flags are
automatically cleared when their interrupt is executed. These kinds of interrupts are BIT, WDT,
TIMER0/1/2/3, I2C, Watch Timer, USART RX, REMOCON, External Interrupt 0/1/2/3 and Pin Change
Interrupt. KEYSCAN, FLASH and Pin Change Interrupts have no flag bit,so these interrupts cannot be
used in polling mode.
10.5 Interrupt Sequence
When a interrupt occurs, the flag is stored to the status register which belongs to the interrupt source.
An interrupt request is preserved until the request is accepted by CPU or cleared to ‘0’ by a reset or
an instruction.
NOTE . The CPU accepts a interrupt request at the last cycle of current instruction. So
instead of executing the instruction being fetched, the CPU executes internally a LCALL instruction
and saves the PC to the stack region. At the same time the interrupt controller hands over the
address of LJMP instruction to the service routine, which is used by the CPU. It takes 3 to 9 cycles to