148
November, 2018 Rev.1.4
load SLA+R/W into the I2CDR and set the START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In
case of 4), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is
‘0’ go to master transmitter section.
9. This is the final step for master receiver function of I
2
C, handling STOP interrupt. The STOP
bit indicates that data transfer between master and slave is over. To clear I2CSR, write
arbitrary value to I2CSR. After this, I
2
C enters idle state.
The processes described above for master receiver operation of I
2
C can be depicted as the following
figure.
From master to slave /
Master command or Data Write
From slave to master
0xxx
Value of Status Register
ACK
Interrupt
, SCL line is held low
Interrupt
after stop command
P
ACK
Arbitration lost as master and
addressed as slave
LOST&
Other master continues
Slave Receiver (0x1D)
or Transmitter (0x1F)
Master
Transmitter
SLA+R
ACK
DATA
Rs
LOST
LOST&
STOP
LOST
S or Sr
SLA+W
Y
N
0x0C
0x85
0x84
0x0C
ACK
STOP
Y
N
0x0D
0x1D
0x45
0x1F
0x44
LOST
P
0x20
P
0x20
Sr
0x44
Figure 11-52 Formats and States in the Master Receiver Mode
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
