November, 2018 Rev.1.4
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3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘1’ go to
master receiver section.
7. 1-Byte of data is being transmitted. During data transfer, bus arbitration continues.
8. This is ACK signal processing stage for data packet transmitted by master. I
2
C holds the SCL
LOW. When I
2
C loses bus mastership while transmitting data arbitrating other masters, the
MLOST bit in I2CSR is set. If then, I
2
C waits in idle state. When the data in I2CDR is
transmitted completely, I
2
C generates TEND interrupt.
I
2
C can choose one of the following cases regardless of the reception of ACK signal from
slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can
receive more data from master. In this case, load data to transmit to I2CDR.
2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the
STOP bit in I2CMR.
3) Master transmits repeated START condition with not checking ACK signal. In this case,
load SLA+R/W into the I2CDR and set the START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of
3), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is ‘1’ go to
master receiver section.
9. This is the final step for master transmitter function of I
2
C, handling STOP interrupt. The
STOP bit indicates that data transfer between master and slave is over. To clear I2CSR, write
arbitrary value to I2CSR. After this, I
2
C enters idle state.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
