November, 2018 Rev.1.4
71
11.3.3 Register Map
Name
Address
Dir
Default
Description
WDTR
8E
H
W
FF
H
Watch Dog Timer Register
WDTCR
8E
H
R
00
H
Watch Dog Timer Counter Register
WDTMR
8D
H
R/W
00
H
Watch Dog Timer Mode Register
Table 11-3 Register Map of WDT
11.3.4 Register Description
WDTR (Watch Dog Timer Register, Write Case)
8E
H
7
6
5
4
3
2
1
0
WDTR7
WDTR 6
WDTR 5
WDTR 4
WDTR 3
WDTR 2
WDTR 1
WDTR 0
W
W
W
W
W
W
W
W
Initial value : FF
H
WDTR[7:0]
Time-out value of WDT counter (=the period of WDT interrupt)
WDT Interrupt Interval = (BIT Interrupt Interval) x (WDTR + 1)
Precaution must be taken when writing this register. To ensure proper operation, the written value,
WDTR should be greater than 01
H
.
WDTCR (Watch Dog Timer Counter Register, Read Case)
8E
H
7
6
5
4
3
2
1
0
WDTCR 7
WDTCR 6
WDTCR 5
WDTCR 4
WDTCR 3
WDTCR 2
WDTCR 1
WDTCR 0
R
R
R
R
R
R
R
R
Initial value : 00
H
WDTCR[7:0]
The value of WDT counter
WDTMR (Watch Dog Timer Mode Register)
8D
H
7
6
5
4
3
2
1
0
WDTEN
WDTRSON
WDTCL
-
-
-
-
WDTIFR
R/W
R/W
R/W
-
-
-
-
R/W
Initial value : 00
H
WDTEN
Enable or disable WDT module
0
Disable
1
Enable
WDTRSON
Decides whether to use WDT interrupt as a reset source or not
0
WDT operates as a free-running 8-bit timer
1
WDT reset is generated when WDT counter overflows
WDTCL
Initialize WDT counter
0
Free runs
1
Reset WDT counter. This bit is auto-cleared after 1 machine
cycle.
WDTIFR
This flag is set when WDT interrupt is generated. This bit is cleared
when the CPU services or acknowledges WDT interrupt or s/w write’0’
to this bit position.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
