126
November, 2018 Rev.1.4
- 1 start bit
- 5, 6, 7, 8 or 9 data bits
- no, even or odd parity bit
- 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit (MSB). If enabled the parity
bit is inserted after the data bits, before the stop bits. A high to low transition on data pin is considered
as start bit. When a complete frame is transmitted, it can be directly followed by a new frame, or the
communication line can be set to an idle state. The idle means high state of data pin. The next figure
shows the possible combinations of the frame formats. Bits inside brackets are optional.
1 data frame consists of the following bits
•
Idle No communication on communication line (TXD/RXD)
•
St Start bit (Low)
•
Dn Data bits (0~8)
•
Parity bit ------------ Even parity, Odd parity, No parity
•
Stop bit(s) ---------- 1 bit or 2 bits
The frame format used by the USART is set by the USIZE[2:0], UPM[1:0] and USBS bits in UCTRL1
register. The Transmitter and Receiver use the same setting.
11.9.7 Parity bit
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result
of the exclusive-or is inverted. The parity bit is located between the MSB and first stop bit of a serial
frame.
P
even
= D
n-1
^ … ^ D
3
^ D
2
^ D
1
^ D
0
^ 0
P
odd
= D
n-1
^ … ^ D
3
^ D
2
^ D
1
^ D
0
^ 1
P
even
: Parity bit using even parity
P
odd
: Parity bit using odd parity
D
n
: Data bit n of the character
Figure 11-38 frame format
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
