Abov MC96FR364B, User Manual

Page: 123 / 194

November, 2018 Rev.1.4 123
11.9.2 Block Diagram
XCKx
XCK
Control
Clock Sync
Logic
UBAUD
RXDx/
MISOx
TXDx/
MOSIx
M
U
X
M
U
X
Tx
Control
Rx
Control
Clock
Recovery
Receive Shift Register
(RXSR)
Data
Recovery
DOR/PE/FE
Checker
UDATA[0]
(Rx)
UDATA[1]
(Rx)
Parity
Generator
Stop bit
Generator
D
E
P
UDATA(Tx)
Transmit Shift Register
(TXSR)
M
U
X
M
U
X
SSx
SS
Control
RXC
TXC
UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL UCTRLx1
ADDRESS : E2
H
/ FA
H
INITIAL VALUE : 0000_0000
B
UDRIE TXCIE RXCIE WAKEIE TXE RXE USARTEN U2X
UCTRLx2
ADDRESS : E3
H
/ FB
H
INITIAL VALUE : 0000_0000
B
MASTER LOOPS DISXCK SPISS - USBS TX8 RX8 UCTRLx3
ADDRESS : E4
H
/ FC
H
INITIAL VALUE : 0000_-000
B
UDRE TXC RXC WAKE SOFTRST DOR FE PE
USTATx
ADDRESS : E5
H
/ FD
H
INITIAL VALUE : 0000_0000
B
SCLK
M
U
X
Rx Interrupt
Tx Interrupt
I
n
t
e
r
n
a
l
B
u
s
L
i
n
e
D
E
P
UMSEL1&UMSEL0
Master
UPM1
UPM0
UMSEL0
Master
UMSEL[1:0]
Baud Rate Generator
Figure 11-35 The Block Diagram of USART