28
November, 2018 Rev.1.4
7.8 USART CHARACTERISTICS
The following table and figure show the timing condition of USART in SPI or Synchronous mode of
operation. The USART is one of peripherals in MC96FR364B.
NOTE1
.
(VDD =3.3V±10%, VSS =0V, TA=-20~+70
℃
)
Parameter
Symbol
NOTE2
MIN
MAX
Unit
System clock period
t
SCLK
83
1000
ns
Clock (XCK) period
t
XCK
4
1028
t
SCLK
Clock (XCK) high time
t
XCKH
2
514
t
SCLK
Clock (XCK) low time
t
XCKL
2
514
t
SCLK
Lead time
Master
Slave
t
LEAD
t
LEAD
0.5 t
XCK
2 t
SCLK
0.5 t
XCK
-
ns
Lag time
Master
Slave
t
LAG
t
LAG
0.5 t
XCK
2 t
SCLK
0.5 t
XCK
-
ns
Data setup time (inputs)
Master
Slave
t
SIM
t
SIS
2
2
2
2
t
SCLK
Data hold time (inputs)
Master
Slave
t
HIM
t
HIS
10
10
-
-
ns
Data setup time (outputs)
Master
Slave
t
SOM
t
SOS
2
2
2
2
t
SCLK
Data hold time (outputs)
Master
Slave
t
HOM
t
HOS
-10
-10
-
-
ns
Disable time
t
DIS
1
2
t
SCLK
Table 7-8 Timing characteristics of USART in SYNC. or SPI mode of operations
NOTE1
In synchronous mode, Lead and Lag time with respect to SS pin is ignored. And the case of UCPHA=0 is
also applied to SPI mode only.
NOTE2
All timing is shown with respect to 20% VDD and 80% VDD.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
