Abov MC96FR364B, User Manual

Page: 103 / 194

November, 2018 Rev.1.4 103
11.5.3 Register Map
Name Address Dir Default Description
WTMR D1
H
R/W 00
H
Watch Timer Mode Register
WTDR1 D4
H
W 3F
H
Watch Timer Data Register 1
WTDR0 D5
H
W FF
H
Watch Timer Data Register 0
WTSR D9
H
R 00
H
Watch Timer Status Register
WTDRH DC
H
W 7F
H
Watch Timer Data Register High
WTCR0H F1
H
R 3F
H
Watch Timer Capture Register0 High
WTCR0L F2
H
R FF
H
Watch Timer Capture Register0 Low
WTCR1H F3
H
R 3F
H
Watch Timer Capture Register1 High
WTCR1L F4
H
R FF
H
Watch Timer Capture Register1 Low
WTCR2H F5
H
R 3F
H
Watch Timer Capture Register2 High
WTCR2L F6
H
R FF
H
Watch Timer Capture Register2 Low
Table 11-10 Register Map of Watch Timer
11.5.4 Register Description
WTMR (Watch Timer Mode Register) D1
H
7 6 5 4 3 2 1 0
WTEN OVFDIS WTCL - - - WTCK1 WTCK0
R/W R/W R/W - - - R/W R/W
Initial value : 00
H
WTEN Enable Watch Timer
0
Disable WT
1 Enable WT
OVFDIS
Control auto clear function of WT when counters overflow.
NOTE1
0 Auto clear counters when overflow
1 Overflow event is ignored
WTCL Clear counter of Watch Timer
0
No operation (Free Run mode)
1 Clear WT counter (Auto-clear after 1 cycle)
WTCK[1:0]
Select clock source of WT (=f
WCK
)
NOTE2
WTCK1 WTCK0 Watch Timer mode IR Capture mode
0 0 f
SCLK
/32 f
SCLK
0 1 f
SCLK
/64 f
SCLK
/2
1 0 f
SCLK
/128 f
SCLK
/3
1 1 f
SCLK
/256 f
SCLK
/4
NOTE1 The overflow means WT_TMR equals to WTDRH, and WTIR equals to WTCR1/0 when WT is in Watch
Timer mode. In IR capture mode, the overflow condition occurs when WTIR equals to WTCR1/0.
NOTE2 f
SCLK
is the frequency of system clock, SCLK.
f
WCK
is the frequency of WTIR counter clock
WTDR1 (Watch Timer Data Register 1) D4
H
7 6 5 4 3 2 1 0
- - WTDR13 WTDR12 WTDR11 WTDR10 WTDR9 WTDR8