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November, 2018 Rev.1.4
11.10.8 Operation
The I
2
C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a
transmission of a START condition. Because the I
2
C is interrupt based, the application software is
free to carry on other operations during a I
2
C byte transfer.
Note that when a I
2
C interrupt is generated, IIF flag in I2CMR register is set, it is cleared by writing
an arbitrary value to I2CSR. When I
2
C interrupt occurs, the SCL line is hold LOW until writing any
value to I2CSR. When the IIF flag is set, the I2CSR contains a value indicating the current state of the
I
2
C bus. According to the value in I2CSR, software can decide what to do next.
I
2
C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode
is configured by a winning master. A more detailed explanation follows below.
11.10.8.1 Master Transmitter
To operate I
2
C in master transmitter, follow the recommended steps below.
1. Enable I
2
C by setting IICEN bit in I2CMR. This provides main clock to the peripheral.
2. Load SLA+W into the I2CDR where SLA is address of slave device and W is transfer
direction from the viewpoint of the master. For master transmitter, W is ‘0’. Note that I2CDR is
used for both address and data.
3. Configure baud rate by writing desired value to both I2CSCLLR and I2CSCLHR for the Low
and High period of SCL line.
4. Configure the I2CSDAHR to decide when SDA changes value from falling edge of SCL. If
SDA should change in the middle of SCL LOW period, load half the value of I2CSCLLR to the
I2CSDAHR.
5. Set the START bit in I2CMR. This transmits a START condition. And also configure how to
handle interrupt and ACK signal. When the START bit is set, 8-bit data in I2CDR is
transmitted out according to the baud-rate.
6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit
address and 1-bit transfer direction is transmitted to target slave device, the master can know
whether the slave acknowledged or not in the 9
th
high period of SCL. If the master gains bus
mastership, I
2
C generates GCALL interrupt regardless of the reception of ACK from the slave
device. When I
2
C loses bus mastership during arbitration process, the MLOST bit in I2CSR is
set, and I
2
C waits in idle state or can be operate as an addressed slave. To operate as a
slave when the MLSOT bit in I2CSR is set, the ACKEN bit in I2CMR must be set and the
received 7-bit address must equal to the SLA bits in I2CSAR. In this case I
2
C operates as a
slave transmitter or a slave receiver (go to appropriate section). In this stage, I
2
C holds the
SCL LOW. This is because to decide whether I
2
C continues serial transfer or stops
communication. The following steps continue assuming that I
2
C does not lose mastership
during first data transfer.
I
2
C (Master) can choose one of the following cases regardless of the reception of ACK signal
from slave.
1) Master receives ACK signal from slave, so continues data transfer because slave can
receive more data from master. In this case, load data to transmit to I2CDR.
2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the
STOP bit in I2CMR.
3) Master transmits repeated START condition with not checking ACK signal. In this case,
load SLA+R/W into the I2CDR and set START bit in I2CMR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
