Abov MC96FR364B, User Manual

Page: 59 / 194

November, 2018 Rev.1.4 59
vector address to the CPU, M8051W and the CPU acknowledges the request at the first cycle of the
next command to jump to the interrupt vector address.
NOTE
command cycle C?P? : L=Last cycle, 1=1
st
cycle or 1
st
phase, 2=2
nd
cycle or 2
nd
phase
10.12 Interrupt Registers
10.12.1 Register Map
Name Address Dir Default Description
IE A8
H
R/W 00
H
Interrupt Enable Register
IE1 A9
H
R/W 00
H
Interrupt Enable Register 1
IE2 AA
H
R/W 00
H
Interrupt Enable Register 2
IE3 AB
H
R/W 00
H
Interrupt Enable Register 3
IP B8
H
R/W 00
H
Interrupt Priority Register
IP1 F8
H
R/W 00
H
Interrupt Proprity Register 1
EIFLAG AC
H
R/W 00
H
External Interrupt Flag Register
EIEDGE AD
H
R/W 00
H
External Interrupt Edge Register
EIPOLA AE
H
R/W 00
H
External Interrupt Polarity Register
EIENAB AF
H
R/W 00
H
External Interrupt Enable Register
Table 10-3 Register Map of Interrupt Controller
10.12.2 Interrupt Enable Register (IE, IE1, IE2, IE3)
There’re 4 interrupt enable registers which are IE, IE1, IE2 and IE3. In IE register, there’s two kinds of
interrupt enable bits called the global interrupt enable bit, EA, and 6 individual interrupt enable bits,
INTnE. Each IE1, IE2 and IE3 register only has 6 individual interrupt enable bits. Totally 16 peripheral
and external interrupts are controlled by these registers.
10.12.3 Interrupt Priority Register (IP, IP1)
As described above, each interrupt enable register has 6 individual interrupt enable bits. So, interrupt
controller itself can deal up to 24 interrupt sources. These 24 sources are classified into 6 groups by 4
sources. Each group can have 4 level of priority through IP and IP1 registers. The level 3 group
interrupt is of the highest priority, and the level 0 group interrupt is of the lowest priority. The initial
values of IP and IP1 registers are 00
H
. By default, the lower numbered interrupt has the higher priority
if group priority is the same. When the group priority is decided by configuring IP and IP1 registers,
among 4 interrupt sources within the group, the lower numbered interrupt has the higher priority.
10.12.4 External Interrupt Flag Register (EIFLAG)
External Interrupt Flag Register shows the status of external interrupts. Each flag is set to ‘1’ when a
port is configured as a external interrupt source, and the port state changes to equal to the interrupt
generating condition according to EIEDGE and EIPOLA register. To clear each flag, write ‘0’ to
corresponding bit position of this register.