November, 2018 Rev.1.4
151
11.10.8.4 Slave Receiver
To operate I
2
C in slave receiver, follow the recommended steps below.
1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00
into I2CSDAHR to make SDA change within one system clock period from the falling edge of
SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is
multiple of number of SCLK coming from I2CSDAHR. When the hold time of SDA is longer
than the period of SCLK, I
2
C (slave) cannot transmit serial data properly.
2. Enable I
2
C by setting IICEN bit and INTEN bit in I2CMR. This provides main clock to the
peripheral.
3. When a START condition is detected, I
2
C receives one byte of data and compares it with SLA
bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I
2
C compares the received data
with value 0x00, the general call address.
4. If the received address does not equal to SLA bits in I2CSAR, I
2
C enters idle state ie, waits
for another START condition. Else if the address equals to SLA bits and the ACKEN bit is
enabled, I
2
C generates SSEL interrupt and the SCL line is held LOW. Note that even if the
address equals to SLA bits, when the ACKEN bit is disabled, I
2
C enters idle state. When
SSEL interrupt occurs and I
2
C is ready to receive data, write arbitrary value to I2CSR to
release SCL line.
5. 1-Byte of data is being received.
6. In this step, I
2
C generates TEND interrupt and holds the SCL line LOW regardless of the
reception of ACK signal from master. Slave can select one of the following cases.
1) No ACK signal is detected (ACKEN=0) and I
2
C waits STOP or repeated START condition.
2) ACK signal is detected (ACKEN=1) and I
2
C can continue to receive data from master.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either
case, a repeated START condition can be detected. For that case, move step 4.
7. This is the final step for slave receiver function of I
2
C, handling STOP interrupt. The STOP bit
indicates that data transfer between master and slave is over. To clear I2CSR, write arbitrary
value to I2CSR. After this, I
2
C enters idle state.
The process can be depicted as following figure when I
2
C operates in slave receiver mode.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
