Abov MC96FR364B, User Manual

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154 November, 2018 Rev.1.4
I2CSR (I
2
C Status Register) 9D
H
7 6 5 4 3 2 1 0
GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK
R R R R R R R R
Initial value : 00
H
GCALL This bit has different meaning depending on whether I 2 C is master or
slave. Note 1)
When I
2 C is a master, this bit represents whether it received AACK
(Address ACK) from slave.
When I
2 C is a slave, this bit is used to indicate general call.
0 No AACK is received (Master mode)
1 AACK is received (Master mode)
0 Received address is not general call address (Slave mode)
1 General call address is detected (Slave mode)
TEND This bit is set when 1-Byte of data is transferred completely. Note 1)
0
1 byte of data is not completely transferred
1 1 byte of data is completely transferred
STOP
This bit is set when STOP condition is detected. Note 1)
0
No STOP condition is detected
1 STOP condition is detected
SSEL This bit is set when I 2 C is addressed by other master. Note 1)
0 I
2
C is not selected as slave
1 I 2 C is addressed by other master and acts as a slave
MLOST
This bit represents the result of bus arbitration in master mode. Note 1)
0
I 2 C maintains bus mastership
1 I
2
C has lost bus mastership during arbitration process
BUSY This bit reflects bus status.
0
I
2
C bus is idle, so any master can issue a START condition
1 I 2 C bus is busy
TMODE This bit is used to indicate whether I 2 C is transmitter or receiver.
0 I 2 C is a receiver
1 I 2 C is a transmitter
RXACK This bit shows the state of ACK signal.
0
No ACK is received
1 ACK is generated at ninth SCL period
Note 1) These bits can be source of interrupt.
When an I 2 C interrupt occurs except for STOP interrupt, the SCL line is hold LOW. To release SCL,
write arbitrary value to I2CSR. When I2CSR is written, the TEND, STOP, SSEL, LOST, RXACK bits
are cleared.