Abov MC96FR364B, User Manual

Page: 6 / 194

MC96FR364B
6 November, 2018 Rev.1.4
List of Figures
Figure 1-1 Device Nomenclature .......................................................................................................... 11
Figure 1-2 OCD Software and Connector............................................................................................. 12
Figure 1-3 E-PGM+ .............................................................................................................................. 13
Figure 1-4 PGMPlusLC-II .................................................................................................................... 14
Figure 1-5 Gang programmer ............................................................................................................... 14
Figure 2-1 Block Diagram of MC96FR364B ....................................................................................... 15
Figure 3-1 28 TSSOP Pinout MC96FR364BR ..................................................................................... 16
Figure 4-1 PKG DIMENSION (28 TSSOP) ......................................................................................... 18
Figure 6-1 General I/O .......................................................................................................................... 21
Figure 6-2 I/O with external interrupt function .................................................................................... 22
Figure 7-1 AC Timing .......................................................................................................................... 27
Figure 7-2 SPI master mode timing (UCPHA = 0, MSB first) ............................................................. 29
Figure 7-3 SPI / Synchronous master mode timing (UCPHA = 1, MSB first) ..................................... 29
Figure 7-4 SPI slave mode timing (UCPHA = 0, MSB first) ............................................................... 30
Figure 7-5 SPI / Synchronous slave mode timing (UCPHA = 1, MSB first)........................................ 30
Figure 7-6 IOL vs VOL ........................................................................................................................ 31
Figure 7-7 IOH vs VOH ....................................................................................................................... 31
Figure 8-1 Program Memory ................................................................................................................ 33
Figure 8-2 DATA MEMORY (IRAM) ................................................................................................. 34
Figure 8-3 Lower 128 Byte of IRAM ................................................................................................... 35
Figure 8-4 PSW Register ...................................................................................................................... 37
Figure 8-5 DATA MEMORY (XRAM) ............................................................................................... 38
Figure 10-1 External Interrupt trigger condition ................................................................................... 52
Figure 10-2 Block Diagram of Interrupt Controller .............................................................................. 53
Figure 10-3 Sequence of Interrupt handling ......................................................................................... 55
Figure 10-4 Effective time of interrupt request after setting IEx registers ........................................... 56
Figure 10-5 Accept of another interrupt request in interrupt service routine ........................................ 56
Figure 10-6 Interrupt Request and Service Procedure .......................................................................... 57
Figure 10-7 Generating branch address to BIT interrupt service routine from vector table ................. 57
Figure 10-8 Processing General registers while an interrupt is serviced .............................................. 58
Figure 10-9 Timing chart for Interrupt Accept and Branch Address Generation ................................. 58
Figure 11-1 Block Diagram of Clock Generator .................................................................................. 65
Figure 11-2 Block Diagram of BIT ...................................................................................................... 67
Figure 11-3 Block Diagram .................................................................................................................. 70
Figure 11-4 WDT Interrupt and Reset Timing ..................................................................................... 72
Figure 11-5 Block Diagram of Timer 0,1 in 8-bit timer/counter mode ................................................ 74
Figure 11-6 Interrupt Period of Timer 0, 1 ........................................................................................... 75
Figure 11-7 Counter Operation of Timer 0, 1 ....................................................................................... 75
Figure 11-8 Block Diagram of Timer 0, 1 in 16-bit Timer/ Counter mode .......................................... 76
Figure 11-9 Block Diagram of Timer 0, 1 in 8-bit Capture mode ........................................................ 78