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11.9.8 USART Transmitter
The USART Transmitter is enabled by setting the TXE bit in UCTRL1 register. When the Transmitter
is enabled, the normal port operation of the TXD(=MOSI) pin is overridden by the serial output pin of
USART. The baud-rate, operation mode and frame format must be setup once before doing any
transmissions. If synchronous or spi operation is used, the clock on the XCK pin will be overridden
and used as transmission clock. If USART operates in spi mode, SS pin is used as SS input pin in
slave mode or can be configured as SS output pin in master mode. This can be done by setting
SPISS bit in UCTRL3 register.
11.9.8.1 Sending TX data
A data transmission is initiated by loading the transmit buffer (UDATA register I/O location) with the
data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift
register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state
or immediately after the last stop bit of the previous frame is transmitted. When the shift register is
loaded with new data, it will transfer one complete frame at the settings of control registers. If the 9-bit
characters are used in asynchronous or synchronous operation mode (USIZE[2:0]=7), the ninth bit
must be written to the TX8 bit in UCTRL3 register before loading transmit buffer (UDATA register).
11.9.8.2 Transmitter flag and interrupt
The USART Transmitter has 2 flags which indicate its state. One is USART Data Register Empty
(UDRE) and the other is Transmit Complete (TXC). Both flags can be interrupt sources.
UDRE flag indicates whether the transmit buffer is ready to be loaded with new data. This bit is set
when the transmit buffer is empty and cleared when the transmit buffer contains data to be
transmitted that has not yet been moved into the shift register. And also this flag can be cleared by
writing ‘0’ to this bit position. Writing ‘1’ to this bit position is prevented.
When the Data Register Empty Interrupt Enable (UDRIE) bit in UCTRL2 register is set and the Global
Interrupt is enabled, USART Data Register Empty Interrupt is generated while UDRE flag is set.
The Transmit Complete (TXC) flag bit is set when the entire frame in the transmit shift register has
been shifted out and there are no more data in the transmit buffer. The TXC flag is automatically
cleared when the Transmit Complete Interrupt service routine is executed, or it can be cleared by
writing ‘0’ to TXC bit in USTAT register.
When the Transmit Complete Interrupt Enable (TXCIE) bit in UCTRL2 register is set and the Global
Interrupt is enabled, USART Transmit Complete Interrupt is generated while TXC flag is set.
11.9.8.3 Parity Generator
The Parity Generator calculates the parity bit for the sending serial frame data. When parity bit is
enabled (UPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first
stop bit of the sending frame.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
