Abov MC96FR364B, User Manual

Page: 91 / 194

November, 2018 Rev.1.4 91
11.4.3 16-bit Timer 3
11.4.3.1 Overview
16-bit Timer 3 is composed of Multiplexer, Timer Data Register High/Low, Timer Register High/Low,
Input Capture Register High/Low, Mode Control Register, PWM Duty High/Low and PWM Period
High/Low Register.
Timer 3 is can be clocked by Carrier Signal(CRF) from Carrier Generator module or by an internal
clock source deriving from clock divider logic where the base clock is SCLK.
When IRCEN bit in IRCC1 is set, Timer 3 operates in IR capture mode. In this mode Timer 3 can
detect the envelope of IR input signal or counts the number of input carrier signal. In envelop
detection mode of operation, the counter value of Timer 3 is captured into timer capture register on
first rising edge of IR input(normally amplified carrier signal) and overflow of WT. When Timer 3 is
used to calculate the number of carrier signal, the rising edge of input carrier becomes the clock
source of Timer 3. For more information about IR capture operation, refer to WT and IRCC section.
11.4.3.2 16-bit Output Compare or Event Counter Mode
When Timer 3 is in Output Compare or Event Counter Mode, timer output is toggled and appears on
P03 port whenever T3(T3H+T3L) matches T3DR(T3DRH+T3DRL). An interrupt can be requested if
enabled and the interrupt flag can be read through T3CR2 register. The initial value of timer output is
‘0’ and output frequency is calculated by the following equation.
) 1 3 ( Value Prescaler 2
Frequency Clock Timer
  

DR T
COMP
f
where f
COMP
is the frequency of timer output. T3DR is concatenated T3DRH+T2DRL. The clock
source of Timer 3 is selected by T3CK[2:0] bits in T3CR register. To observe timer output via port, set
T3_PE bit in T3CR2 register to ‘1’.