102
November, 2018 Rev.1.4
÷
3
f
SCLK
P
r
e
s
c
a
l
e
r
MUX
÷2
÷
4
14-bit Up Counter
(WTIR)
WTMR
f
WCK
÷1
CAP1EN
WTEN OVFDIS WTCL
-
-
-
WTCK1 WTCK0
WTCR0H/L
WTCR1H/L
WTDR1:WTDR0
D Q
CP
r
RESETB
WTIF
SCLK
OVF = T
WCK
x
WTIR
INT_ACK
Write
‘
0
’
to WTSR
IRCC1
IRCEN
-
-
-
-
-
SINGLE
PHASE
WTCR2H/L
WTCL
WTCL
WTCL
CAP0EN
CAP2EN
MUX
CAP0/1/2EN (=Capture &
WTIR Clear source)
14
14
14
capture0
capture2
WT
Sync
start
WT
clear
WT
clear
WT
clear
WT
clear
WT
clear
WT
clear
WT Overflow
(WT
stop
)
Timer2 captures when T2EDGE[1] = 1
Timer3 captures when T3EDGE[1] = 1
SENSOR Input
(P31)
WTIR Counter
WT Output
capture1
capture1
capture0
capture2
Capture event for Timer 2 or Timer 3
Timer2 captures when T2EDGE[0] = 1
Timer3 captures when T3EDGE[0] = 1
Capture sequence is decided by SINGLE
and PHASE bits in IRCC1 register
Figure 11-25 Block Diagram of Watch Timer in IR capture mode
Figure 11-26 Timing Diagram of Watch Timer in IR capture mode
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
