November, 2018 Rev.1.4
177
15.3 Register Map
Name
Address
Dir
Default
Description
FMR
E1
H
R/W
00
H
FLASH Mode Register
FARH
E9
H
R/W
00
H
FLASH Address Register High
FARM
EA
H
R/W
00
H
FLASH Address Register Middle
FARL
EB
H
R/W
00
H
FLASH Address Register Low
FCR
EC
H
R/W
03
H
FLASH Control Register
FSR
ED
H
R/W
80
H
F LASH Status Register
FTCR
EE
H
R/W
00
H
F LASH Time Control Register
CSUMH
2F06
H
R
00
H
FLASH Read Checksum Register High
CSUMM
2F07
H
R
00
H
FLASH Read Checksum Register Middle
CSUML
2F0F
H
R
00
H
FLASH Read Checksum Register Low
FSLBAx
2F61
H
~2F62
H
R/W
00
H
F LASH Secure Lock Base Address Register
FSLTAx
2F64
H
~2F65
H
R/W
00
H
F LASH Secure Lock Top Address Register
FSUBAx
2F67
H
~2F68
H
R/W
00
H
F LASH Secure Unlock Base Address Register
FSUTAx
2F6A
H
~2F6B
H
R/W
00
H
F LASH Secure Unlock Top Address Register
FSCTRL
2F6C
H
R/W
00
H
F LASH Secure Control Register
PageBuffer
8000
H
~803F
H
R/W
FLASH Page Buffer @XSFR
Table 15-1 Register Map of FLASH Memory Controller
Bank0
(64Kbytes)
0000
H
FFFF
H
8KB
16KB
32KB
1FFF
H
3FFF
H
7FFF
H
8KB
0000
H
256B
256B
Interrupt table
Boot Code Area
2KB
512B
1KB
0FFF
H
00FF
H
01FF
H
03FF
H
07FF
H
4KB
1FFF
H
Boot Area Size
BSIZE[1:0] = 00
512B (0000
H
~ 01FF
H
)
= 01
1024B (0000
H
~ 03FF
H
)
= 10
2048B (0000
H
~ 07FF
H
)
= 11
4096B (0000
H
~ 0FFF
H
)
Figure 15-1 Program Memory Address Space
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...