64
November, 2018 Rev.1.4
EDGEnF
Selects the trigger mode of each external interrupt pin. Trigger
mode is also affected by the EDGEnR bit.
0
External interrupt is triggered by level (default)
1
External interrupt is triggered by a falling edge
When EDGEnR and EDGEnF bits are set at the same time, an
external interrupt is triggered by both rising and falling edge.
EIPOLA (External Interrupt Polarity Register)
AE
H
7
6
5
4
3
2
1
0
-
-
-
--
POLA3
POLA2
POLA1
POLA0
R/W
R/W
R/W-
R/W
R/W
R/W
R/W
R/W
Initial value : 00
H
POLA[3:0]
Selects the trigger level of external interrupt, high or log level.
When configured as level trigger mode
0
External interrupt is triggered by a high level (default)
1
External interrupt is triggered by a low level
EIENAB (External Interrupt Enable Register)
AF
H
7
6
5
4
3
2
1
0
-
-
-
--
ENAB3
ENAB2
ENAB1
ENAB0
R/W-
R/W-
R/W-
R/W
R/W
R/W
R/W
R/W
Initial value : 00
H
ENAB[3:0]
Configure each port pin as external interrupt pin input
0
The port is not used for external interrupt (default)
1
The port is used for external interrupt
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
