November, 2018 Rev.1.4
97
CDR3L, PWM3DRL and T3L registers share peripheral address. When PWM mode is enabled,
reading this address gives PWM3DRL. When PWM mode is disabled, reading this address gives
CDR3L in Capture Mode or T3L in Output Compare Mode. Writing this address alters PWM3DRL
when PWM3E bit is ‘1’. When PWM mode is disabled, writing this address alters T3DRL.
T3CR (Timer 3 Mode Control Register)
CA
H
7
6
5
4
3
2
1
0
EC3E
PWM3E
CAP3
T3CK2
T3CK1
T3CK0
T3CN
T3ST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00
H
EC3E
Enable event counter mode of Timer 3.
0
Timer 3 is a normal counter.
1
Timer 3 is an event counter clocked by EC3.
PWM3E
Enable PWM function of Timer 3
0
Timer 3 is Normal Timer/Counter
1
Timer 1 is PWM
CAP3
Selects operating mode of Timer 3
0
Timer/Counter mode
1
Capture mode
T3CK[2:0]
Selects the clock source of Timer 3.
NOTE
T3CK2 T3CK1
T3CK0
Timer 3 clock
0
0
0
f
SCLK
0
0
1
f
SCLK
/2^1
0
1
0
f
SCLK
/2^2
0
1
1
f
SCLK
/2^3
1
0
0
f
SCLK
/2^4
1
0
1
f
SCLK
/2^6
1
1
0
f
SCLK
/2^8
1
1
1
CRF (Carrier)
T3CN
Decides whether to pause or continue counting
0
Pause counting temporarily
1
Continue to count
T3ST
Decides whether to start or stop counter
0
Stops counting
1
Clear counter and starts up-counting
NOTE
f
SCLK
is the frequency of internal operating clock, SCLK.
T3CR2 (Timer 3 Mode Control Register 2)
C9
H
7
6
5
4
3
2
1
0
T3REQ
T2REQ
T1REQ
T0REQ
-
-
T3_PE
POL3
R
R
R
R
-
-
R/W
R/W
Initial value : 00
H
T3REQ
Timer 3 Interrupt Flag
NOTE
0
Timer 3 interrupt not occurred
1
Timer 3 interrupt occurred
T2REQ
Timer 2 Interrupt Flag
NOTE
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
