November, 2018 Rev.1.4
81
Resolution
Frequency
T1CK[1:0]=00 (125ns) T1CK[1:0]=01 (250ns) T1CK[1:0]=10 (2us)
10-bit
7.8KHz
3.9KHz
0.49KHz
9-bit
15.6KHz
7.8KHz
0.98KHz
8-bit
31.2KHz
15.6KHz
1.95KHz
7-bit
62.4KHz
31.2KHz
3.91KHz
Table 11-5 PWM Frequency vs. Resolution (In case frequency of SCLK(=f
SCLK
) is 8MHz)
The POL bit in T1CR register determines the polarity of PWM waveform. Setting POL=1 makes PWM
waveform high for duty value. In other case, PWM waveform is low for duty value.
P
r
e
s
c
a
l
e
r
MUX
T0 Clock
Source
SCLK
T1CN
T1ST
T1CK[1:0]
2
÷1
÷2
÷16
8-bit Timer1 PWM Period Register
8-bit Timer1
C 2-bit
Clear
Comparator
PWM1PR
(8-bit)
2 Bit
T1
(8-bit)
[B5
H
]
[B6
H
]
PWM1HR[3:2]
S Q
R
PWM1DR
(8-bit)
PWM1HR[1:0]
Comparator
[B6
H
]
POL1
16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN
T1ST
T1CR
X
0
1
0
X
X
X
X
ADDRESS : B4
H
INITIAL VALUE : 0000_0000
B
PWM1DR
(8-bit)
[B6
H
]
PWM1
POL
T1_PE
-
-
-
PW1H3 PW1H2 PW1H1 PW1H0
PWM1HR
1
-
-
-
X
X
X
X
ADDRESS : B7
H
INITIAL VALUE : 0---_0000
B
Slave
Master
T1_PE
Period High
Duty High
Figure 11-13 Block Diagram of Timer 1 in PWM mode
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...