November, 2018 Rev.1.4
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11.9.4 External Clock (XCK)
External clocking is used by the synchronous or spi slave modes of operation.
External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability.
The output from the synchronization logic must then pass through an edge detector before it can be
used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and
therefore the maximum frequency of the external XCK pin is limited by the following equation.
fXCK =
fSCLK
4
where fXCK is the frequency of XCK and fSCLK is the frequency of main system clock (SCLK).
11.9.5 Synchronous mode operation
When synchronous or spi mode is used, the XCK pin will be used as either clock input (slave) or clock
output (master). The dependency between the clock edges and data sampling or data change is the
same. The basic principle is that data input on RXD (MISO in spi mode) pin is sampled at the opposite
XCK clock edge of the edge in the data output on TXD (MOSI in spi mode) pin is changed.
The UCPOL bit in UCTRL1 register selects which XCK clock edge is used for data sampling and
which is used for data change. As shown in the figure below, when UCPOL is zero the data will be
changed at rising XCK edge and sampled at falling XCK edge.
11.9.6 Data format
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits),
and optionally a parity bit for error checking.
The USART supports all 30 combinations of the following as valid frame formats.
XCK
TXD/RXD
UCPOL = 1
TXD/RXD
XCK
UCPOL = 0
Sample
Sample
Figure 11-37 Synchronous Mode XCKn Timing.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
