52
November, 2018 Rev.1.4
10.2 External Interrupt
The External Interrupts are triggered by the INT0, INT1, INT2, INT3 pins. The External Interrupts can
be triggered by a falling or rising edge or a low or high level. The trigger mode and trigger level is
controlled by External Interrupt Edge Register (EIEDGE) and External Interrupt Polarity Register
(EIPOLA). When the external interrupt is enabled and is configured as level triggered, the interrupt will
trigger as long as the pin is held low or high. External interrupts are detected asynchronously. This
implies that these interrupts can be used for wake-up sources from stop mode. The interrupt requests
from INT0, INT1, INT2, INT3 pins can be monitored through the External Interrupt Flag Register
(EIFLAG).
2
2
2
2
EIFLAG1
INT1 Interrupt
EIFLAG0
INT0 Interrupt
EIFLAG3
INT3 Interrupt
EIFLAG2
INT2 Interrupt
EIEDGE, EIPOLA
[AD
H
] EIEDGE
[AE
H
] EIPOLA
INT0 Pin
(P36)
INT1 Pin
(P37)
INT2 Pin
(P21)
INT3 Pin
(P22)
Figure 10-1 External Interrupt trigger condition
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
