November, 2018 Rev.1.4
29
NOTE
When in Synchronous mode, the START bit becomes MSB and the 1
st
or 2
nd
STOP bit becomes LSB.
t
LAG
XCKx
(UCPOL=1)
(OUTPUT)
MOSI/TX1
(OUTPUT)
MISO/RX1
(INPUT)
t
XCK
0.8VDD
0.2VDD
t
HOM
XCKx
(UCPOL=0)
(OUTPUT)
t
XCKH
t
XCKL
/SS0
(OUTPUT)
MSB
LSB
LSB
MSB
t
SIM
t
HIM
t
DIS
t
LEAD
t
SOM
BIT 6 … 1
BIT 6 … 1
XCK0
(UCPOL=1)
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
t
XCK
0.8VDD
0.2VDD
t
SOM
XCK0
(UCPOL=0)
(OUTPUT)
t
XCKH
t
XCKL
/SS0
(OUTPUT)
MSB
LSB
LSB
MSB
t
SIM
t
HIM
t
DIS
t
LAG
t
LEAD
t
SOM
BIT 6 … 1
BIT 6 … 1
t
HOM
Figure 7-2 SPI master mode timing (UCPHA = 0, MSB first)
Figure 7-3 SPI / Synchronous master mode timing (UCPHA = 1, MSB first)
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
