Abov MC96FR364B, User Manual

Page: 192 / 194

192 November, 2018 Rev.1.4
17. APPENDIX
A. Instruction Table
The instruction length of M8051W can be 1, 2, or 3 bytes as listed in the following table. It takes 1, 2,
or 4 cycles for the CPU to execute an instruction. The cycle is composed of two internal clock periods.
ARITHMETIC
Mnemonic Description Bytes Cycles Hex code
ADD A,Rn Add register to A
1 1
28-2F
ADD A,dir Add direct byte to A 2 1 25
ADD A,@Ri Add indirect memory to A 1 1 26-27
ADD A,#data Add immediate to A 2 1 24
ADDC A,Rn Add register to A with carry 1 1 38-3F
ADDC A,dir Add direct byte to A with carry 2 1 35
ADDC A,@Ri Add indirect memory to A with carry 1 1 36-37
ADDC A,#data Add immediate to A with carry 2 1 34
SUBB A,Rn Subtract register from A with borrow 1 1 98-9F
SUBB A,dir Subtract direct byte from A with borrow 2 1 95
SUBB A,@Ri Subtract indirect memory from A with borrow 1 1 96-97
SUBB A,#data Subtract immediate from A with borrow 2 1 94
INC A Increment A 1 1 04
INC Rn Increment register 1 1 08-0F
INC dir Increment direct byte 2 1 05
INC @Ri Increment indirect memory 1 1 06-07
DEC A Decrement A 1 1 14
DEC Rn Decrement register 1 1 18-1F
DEC dir Decrement direct byte 2 1 15
DEC @Ri Decrement indirect memory 1 1 16-17
INC DPTR Increment data pointer 1 2 A3
MUL AB Multiply A by B 1 4 A4
DIV AB Divide A by B 1 4 84
DA A Decimal Adjust A 1 1 D4
LOGICAL
Mnemonic Description Bytes Cycles Hex code
ANL A,Rn AND register to A
1 1
58-5F
ANL A,dir AND direct byte to A 2 1 55
ANL A,@Ri AND indirect memory to A 1 1 56-57
ANL A,#data AND immediate to A 2 1 54
ANL dir,A AND A to direct byte 2 1 52
ANL dir,#data AND immediate to direct byte 3 2 53
ORL A,Rn OR register to A 1 1 48-4F
ORL A,dir OR direct byte to A 2 1 45
ORL A,@Ri OR indirect memory to A 1 1 46-47
ORL A,#data OR immediate to A 2 1 44
ORL dir,A OR A to direct byte 2 1 42
ORL dir,#data OR immediate to direct byte 3 2 43
XRL A,Rn Exclusive-OR register to A 1 1 68-6F
XRL A,dir Exclusive-OR direct byte to A 2 1 65