86
November, 2018 Rev.1.4
W
-
-
-
W
W
W
W
Initial value : 00
H
T1_PE
Controls whether to output Timer 1 output or not through I/O pin. Note
this bit is write-only.
0
Timer 1 output does not come out through I/O pin
1
Timer 1 output overrides the normal port functionality of I/O pin
PW1H[3:2]
High (bit [9:8]) value of PWM period
PW1H[1:0]
High (bit [9:8]) value of PWM duty
When Timer 1 operates in PWM mode, PW1H[3:2] and T1PP constitute the period of PWM,
PW1H[1:0] and T1PD constitute the duty of PWM.
11.4.2 16-bit Timer 2
11.4.2.1 Overview
16-bit Timer 2 is composed of Multiplexer, Timer Data Register High/Low, Timer Register High/Low
and Mode Control Register.
Timer 2 is clocked by Carrier Signal (CRF) from Carrier Generator module or by an internal clock
source deriving from clock divider logic where the base clock is SCLK. This timer supports output
compare(Timer/Counter) and input capture function.
When IRCEN bit in IRCC1 is set, Timer 2 operates in IR capture mode. In this mode Timer 2 can
detect the envelope of IR input signal or counts the number of input carrier signal. In envelop
detection mode of operation, the counter value of Timer 2 is captured into timer capture register on
first rising edge of IR input(normally amplified carrier signal) and overflow of WT. When Timer 2 is
used to calculate the number of carrier signal, the rising edge of input carrier becomes the clock
source of Timer 2. For more information about IR capture operation, refer to WT and IRCC section.
11.4.2.2 16-bit Output Compare or Event Counter Mode
When Timer 2 is in Output Compare or Event Counter Mode, timer output is toggled and appears on
P02 port whenever T2(T2H+T2L) matches T2DR(T2DRH+T2DRL). An interrupt can be requested if
enabled and the interrupt flag can be read through T3CR2 register. The initial value of timer output is
‘0’ and output frequency is calculated by the following equation.
)
1
2
(
Value
Prescaler
2
Frequency
Clock
Timer
DR
T
COMP
f
where f
COMP
is the frequency of timer output, T2DR is concatenated T2DRH+T2DRL. The clock
source of Timer 2 is selected by T2CK[2:0] bits in T2CR register. To observe timer output via port, set
T2_PE bit in T2CR register to ‘1’.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
