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November, 2018 Rev.1.4
for (i=0; I < FLASH_PBUFF_SIZE; i++) {
pagerom[i] = 0x00;
}
// Step 5
FARL = (unsigned char) addr;
FARM = (unsigned char) (addr>>8);
// Step 8
FECR = 0x0B;
// Step 9 : It is optional because the CPU clock halts while in program or erase operation.
while(FESR>>7 == 0x00);
}
void
flash_page_
write(unsigned int addr, unsigned char *wdata)
{
int i;
unsigned char temp;
int addr_index;
// Step 1
FETCR = PGMTIME;
// Step 3
page_buffer_reset();
// Step 4
for (i=0; I < FLASH_PBUFF_SIZE; i++) {
pagerom[i] = wdata[i];
}
// Step 5
FARL = (unsigned char) addr;
FARM = (unsigned char) (addr>>8);
// Step 8
FECR = 0x0D;
// Step 9 : It is optional because the CPU clock halts while in program or erase operation.
while(FESR>>7 == 0x00);
}
void page_buffer_reset()
{
FECR = 0x00;
}
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
