106
November, 2018 Rev.1.4
captured to this register at the second falling edge (when PHASE
bit is ‘0’) or second rising edge (when PHASE bit is ‘1’) of input
carrier signal. This register is initialized
by setting WTCL bit in
WTMR.
The WT interrupt is requested only when overflow condition occurs. That is when WT is in IR capture
mode, the interrupt is not issued even when capture event is generated.
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
