November, 2018 Rev.1.4
73
11.4 TIMER/PWM
11.4.1 8-bit
Timer/Event Counter 0, 1
11.4.1.1 Overview
Timer 0 and Timer 1 can be used as either separate 8-bit Timer/Counter or one combined 16-bit
Timer/Counter. Each 8-bit Timer/Event Counter module has a multiplexer, 8-bit timer data register, 8-
bit counter register, mode control register, input capture register and comparator. For PWM mode of
operation, Timer 1 has additional registers which are PWM1PR, PWM1DR and PWM1HR.
Timer 0 and Timer 1 have 5 operating modes as following.
- two separate 8-bit Timer/Counter Mode
- two separate 8-bit Capture Mode
- 16-bit Timer/Counter Mode
- 16-bit Capture Mode
- PWM Mode
Timer 0, 1 are clocked by an internal an external clock source (EC0). The clock source is selected by
clock select logic which is controlled by the clock select bits(T0CK[2:0], T1CK[2:0]) located in the
T0CR and T1CR registers. By configuring T1CK[2:0] bits, Timer 1 can be clocked by the clock source
used for Timer 0 or by its own divided clock
NOTE
. Internal clock source is derived from the divider logic
of each timer module. In Capture Mode, the counter value is captured into each Input Capture
Register when a external interrupt condition is generated on INT0 or INT1 pins. In 8/16-bit
Timer/Counter Mode, Timer 0 compares counter value with the value in timer data register and when
counter reaches to the compare value, the timer output is toggled internally. When the T0_PE bit in
T0CR register is set, the timer output overrides the normal port functionality of the I/O pin it is
connected to. Timer 1 operates similar to Timer 0, and in addition can generate PWM wave form
when configured as PWM mode. And the Timer 1 output or PWM output appears on T1/PWM1 pin.
NOTE
SCLK is internal operating clock, which is the output of clock divider logic. The input source of clock divider
is XINCLK, the output of main oscillator. The divide ratio can be selected from DIV[1:0] bits in SCCR register and
the default frequency is that of main oscillator output, XINCLK. For more information about clock scheme, refer to
chapter 11.1.
The next table shows register setting for each timer operating mode.
16 Bit CAP0 CAP1 PWM1E T0CK[2:0] T1CK[1:0] T0/1_PE
Timer 0
Timer 1
0
0
0
0
XXX
XX
00
8-bit Timer
8-bit Timer
0
0
1
0
111
XX
00
8-bit Event Counter
8-bit Capture
0
1
0
0
XXX
XX
01
8-bit Capture
8-bit Compare Output
0
0
0
1
XXX
XX
11
8-bit Timer/Counter
10-bit PWM
1
0
0
0
XXX
11
00
16-bit Timer
1
0
0
0
111
11
00
16-bit Event Counter
1
1
1
0
XXX
11
00
16-bit Capture
1
0
0
0
XXX
11
01
16-bit Compare Output
Table 11-4 Operating modes of Timer 0, 1
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
