November, 2018 Rev.1.4
93
11.4.3.4 Carrier Counting Mode
Carrier Counting Mode is enabled by setting T3IR bit in IRCC2 register. This mode of operation is only
available when IRCEN bit in IRCC1 register is set. The clock source is the rising edge of input carrier
signal. Like output compare mode, when T3H+T3L reaches to the value of T3DRH+T3DRL, an
interrupt is requested if enabled.
EC3E PWM3
E
CAP3
T3CK2 T3CK1 T3CK0 T3CN
T3ST
T3CR
X
X
1
X
X
X
X
X
ADDRESS : CA
H
INITIAL VALUE : 0000_0000
B
[CC
H
]
INT3IF
INT3
Interrupt
16-bit Counter
16-bit Capture Register
T3CN
Clear
[CB
H
]
T3ST
INT3
EIEDGE[7:6]
T3H(8-bit)
T3L(8-bit)
CDR3H(8-bit)
CDR3L(8-bit)
[CC
H
]
[CB
H
]
T3REQ T2REQ T1REQ
T0REQ
-
-
T3_PE
POL
T3CR2
X
X
X
X
X
X
X
X
ADDRESS : C9
H
INITIAL VALUE : 0000_--00
B
÷64
÷16
P
r
e
s
c
a
l
e
r
MUX
÷1
÷2
÷4
÷8
SCLK
T3CK[2:0]
3
÷256
EC3 (or
IRSensor)
CRF
T3IF/
WTIF
T3 or WT
Interrupt
T3EDGE[1:0]
IRCAP3
WT Out
IRCAP3 = T3EDGE[1:0] != 00
B
0
1
Figure 11-20 Block Diagram of Timer 3 in Capture Mode
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
