134
November, 2018 Rev.1.4
UCTRL12
FB
H
R/W
00
H
USART1 Control 2 Register
UCTRL13
FC
H
R/W
00
H
USART1 Control 3 Register
USTAT1
FD
H
R
80
H
USART1 Status Register
UBAUD1
FE
H
R/W
FF
H
USART1 Baud Rate Generation Register
UDATA1
FF
H
R/W
FF
H
USART1 Data Register
Table 11-18 Register map of USART
11.9.12 Register Description
UCTRLx1 (USART0[1] Control 1 Register)
E2
H
/ FA
H
7
6
5
4
3
2
1
0
UMSEL1
UMSEL0
UPM1
UPM0
USIZE2
USIZE1
UDORD
USIZE0
UCPHA
UCPOL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00
H
UMSEL[1:0]
Selects operation mode of USART
UMSEL1
UMSEL0
Operating Mode
0
0
Asynchronous Mode (Normal Uart)
0
1
Synchronous Mode (Synchronous Uart)
1
0
Reserved
1
1
SPI Mode
UPM[1:0]
Selects Parity Generation and Check methods
UPM1
UPM0
Parity mode
0
0
No Parity
0
1
Reserved
1
0
Even Parity
1
1
Odd Parity
USIZE[2:0]
When in asynchronous or synchronous mode of operation, selects the
length of data bits in frame.
USIZE2
USIZE1 USIZE0
Data length
0
0
0
5 bit
0
0
1
6 bit
0
1
0
7 bit
0
1
1
8 bit
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
9 bit
UDORD
This bit is in the same bit position with USIZE1. In SPI mode, when set
to one the MSB of the data byte is transmitted first. When set to zero
the LSB of the data byte is transmitted first.
0
LSB First
1
MSB First
UCPOL
Selects polarity of XCK in synchronous or spi mode
0
TXD(=MOSI) change @Rising Edge, RXD(=MISO) change
@Falling Edge
1
TXD(=MOSI) change @ Falling Edge, RXD(=MISO) change @
Rising Edge
UCPHA
This bit is in the same bit position with USIZE0. In SPI mode, along
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
