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November, 2018 Rev.1.4
When the Receiver is enabled (RXE=1), the clock recovery logic tries to find a high to low transition
on the RXD(=MISO) line, the start bit condition. After detecting high to low transition on RXD(=MISO)
line, the clock recovery logic uses samples 8,9, and 10 for Normal mode, and samples 4, 5, and 6 for
Double Speed mode to decide if a valid start bit is received. If more than 2 samples have logical low
level, it is considered that a valid start bit is detected and the internally generated clock is
synchronized to the incoming data frame. And the data recovery can begin. The synchronization
process is repeated for each start bit.
As described above, when the Receiver clock is synchronized to the start bit, the data recovery can
begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic
samples 16 times for each incoming bits for Normal mode and 8 times for Double Speed mode. And
uses sample 8, 9, and 10 to decide data value for Normal mode, samples 4, 5, and 6 for Double
Speed mode. If more than 2 samples have low levels, the received bit is considered to a logic 0 and
more than 2 samples have high levels, the received bit is considered to a logic 1. The data recovery
process is then repeated until a complete frame is received including the first stop bit. The decided bit
value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit
of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find
start bit.
The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more
samples of 3 center values have high level, correct stop bit is detected, else a Frame Error flag is set.
After deciding first stop bit whether a valid stop bit is received or not, the Receiver goes idle state and
monitors the RXD(=MISO) line to check a valid high to low transition is detected (start bit detection).
RXD
1
2
3
4
5
6
7
8
9
10
11 12
13
STOP 1
1
2
3
4
5
6
7
Sample
(U2X = 0)
Sample
(U2X = 1)
(A)
(B)
(C)
RXD
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15
16
1
BIT n
1
2
3
4
5
6
7
8
1
Sample
(U2X = 0)
Sample
(U2X = 1)
Figure 11-40 The Sampling of Data and Parity Bit
Figure 11-41 Stop Bit Sampling and Next Start Bit Sampling
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
