94
November, 2018 Rev.1.4
The EC3E and CAP3 bit in T3CR register should be cleared to ‘0’ for proper operation.
11.4.3.5 PWM Mode
Timer 3 supports simple PWM waveform generating function by setting PWM3E bit in T3CR register.
As Timer 3 is 16-bit wide, the PWM resolution is also 16-bit depth. To output the PWM waveform
through T3/PWM3 pin, the T3_PE bit in T3CR2 register is to be set. The period and duty of PWM
waveform are decided by PWM3PRH, PWM3PRL, PWM3DRH and PWM3DRL registers. The
equation to calculate period and duty is as follows.
PWM Period = [ PWM3PRH, PWM3PRL ] X Timer 3 Clock Period
PWM Duty = [ PWM3DRH, PWM3DRL ] X Timer 3 Clock Period
Resolution
Frequency
T3CK[2:0]=000 (250ns) T3CK[2:0]=001 (500ns) T3CK[2:0]=011 (2us)
16-bit
60.938Hz
30.469Hz
7.617Hz
15-bit
121.87Hz
60.938Hz
15.234Hz
10-bit
3.9KHz
1.95KHz
0.49KHz
9-bit
7.8KHz
3.9KHz
0.98KHz
8-bit
15.6KHz
7.8KHz
1.95KHz
Table 11-8 PWM Frequency vs. Resolution (In case of f
SCLK
=4MHz)
The POL bit in T3CR register determines the polarity of PWM waveform. Setting POL=1 makes the
PWM waveform high for duty value. In other case, PWM waveform is low for duty value.
T3CR
0
X
0
X
X
X
X
X
ADDRESS : CA
H
INITIAL VALUE : 0000_0000
B
T3CN
IRSensor
[CE
H
]
T3IF
Timer3
Interrupt
16-bit Timer3 Counter
16-bit Timer3 Data Register
Clear
[CC
H
]
Comparator
T3ST
T3H
(8-bit)
T3L
(8-bit)
T2DRH
(8-bit)
T2DRL
(8-bit)
[CB
H
]
[CD
H
]
EC3E PWM3
E
CAP3 T3CK2 T3CK1 T3CK0 T3CN
T3ST
IRCC2
1
X
X
X
X
X
X
X
ADDRESS : DF
H
INITIAL VALUE : 0000_0000
B
T3IR
T2IR
-
-
T3EDG
E1
T3EDG
E9
T2EDG
E1
T2EDG
E0
Figure 11-21 Block Diagram of Timer 3 in Carrier Counting Mode
Summary of Contents for MC96FR364B
Page 17: ...MC96FR364B November 2018 Rev 1 4 17 4 PACKAGE DIMENSION...
Page 18: ...MC96FR364B 18 November 2018 Rev 1 4 Figure 4 1 PKG DIMENSION 28 TSSOP...
Page 23: ...MC96FR364B November 2018 Rev 1 4 23 6 3 REMOUT Port Data PAD VDD Figure 6 3 REMOUT port...
Page 69: ...November 2018 Rev 1 4 69 Initial value 00H BIT 7 0 BIT counter value...
