4.2.5.2.2 WS1 Mode
In general, when accessing a peripheral, the latency in number of HFCLK cycles, not including master arbitration, is given by:
N
bus cycles
= N
slave cycles
∙ f
HFCLK
/f
PERCLK
+ 2, best-case write accesses
N
bus cycles
= N
slave cycles
∙ f
HFCLK
/f
PERCLK
+ 1, best-case read accesses
N
bus cycles
= (N
slave cycles
+ 1) ∙ f
HFCLK
/f
PERCLK
+ 1, worst-case write accesses
N
bus cycles
= (N
slave cycles
+ 1) ∙ f
HFCLK
/f
PERCLK
, worst-case read accesses
where N
slave cycles
is the throughput of the slave's bus interface in number of PERCLK cycles per transfer, including any wait cycles
introduced by the slave.
Figure 4.7. Bus Access Latency (General Case)
Note that a latency of
1
cycle corresponds to
0
wait states.
Additionally, for back-to-back accesses to the same peripheral, the throughput in number of cycles per transfer is given by:
N
bus cycles
= max{f
HFCLK
/f
PERCLK
, 2} + N
slave cycles
∙ f
HFCLK
/f
PERCLK
, write accesses
N
bus cycles
= (N
slave cycles
+ 1) ∙ f
HFCLK
/f
PERCLK
, read accesses
Figure 4.8. Bus Access Throughput (Back-to-Back Transfers)
Lastly, in the highest performing case, where PERCLK equals HFCLK and the slave does not introduce any additional wait states, the
access latency in number of cycles is given by:
N
bus cycles
= 3, write accesses
N
bus cycles
= 2, read accesses
Figure 4.9. Bus Access Latency (Max Performance)
4.2.5.2.3 Core Access Latency
Note that the cycle counts in the equations above is in terms of the HFCLK. When the core is prescaled from the bus clock, the core will
see a reduced number of latency cycles given by:
N
core cycles
= ceiling( N
bus cycles
∙ f
HFCORECLK
/f
HFCLK
)
where master arbitration is not included.
Figure 4.10. Core Access Latency
Reference Manual
Memory and Bus System
silabs.com
| Building a more connected world.
Rev. 1.1 | 50
