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8.3 Functional Description
The Linked DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement
from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of
data or avoiding frequent interrupts to service peripherals needing more data or having available data. It can also be used to reduce the
system energy consumption by making the LDMA work autonomously with some EM2/3 peripherals for data transfer without having to
wake up the processor core from sleep.
The Linked DMA Controller has 8 independent channels. Each of these channels can be connected to any of the available peripheral
DMA transfer request input sources by writing to the channel configuration registers, see
. In addition, each
channel can also be triggered directly by software, which is useful for memory-to-memory transfers.
The channel descriptors determine what the Linked DMA Controller will do when it receives DMA transfer request. The initial descriptor
is written directly to the LDMA's channel registers. If desired, the initial descriptor can link to additional linked descriptors stored in mem-
ory (RAM or Flash). Alternatively, software may also load the initial descriptor by writing the descriptor address to the LDMA_CHx_LINK
register and then setting the corresponding bit the LDMA_LINKLOAD register.
Before enabling a channel, the software must take care to properly configure the channel registers including the link address and any
linked descriptors. When a channel is triggered, the Linked DMA Controller will perform the memory transfers as specified by the de-
scriptors. A descriptor contains the memory address to read from, the memory address to write to, link address of the next descriptor,
the number of bytes to be transferred, etc. The channel descriptor is described in detail in
8.3.7 Channel Descriptor Data Structure
The Linked DMA Controller supports both fixed priority and round robin arbitration. The number of fixed and round robin channels is
programmable. For round robin channels, the number of arbitration slots requested for each channel is programmable. Using this
scheme, it is possible to ensure that timing-critical transfers are serviced on time.
DMA transfers take place by reading a block of data at a time from the source, storing it in the LDMA’s local FIFO, then writing the block
out to the destination from the FIFO. Interrupts may optionally be signaled to the CPU’s interrupt controller at the end of any DMA trans-
fer or at the completion of a descriptor if the DONEIFSEN bit is set. An AHB error will always generate an interrupt.
8.3.1 Channel Descriptor
Each DMA channel has descriptor registers. A transfer can be initialized by software writing to the registers or by the DMA itself copying
a descriptor from RAM to memory. When using a linked list of descriptors the first descriptor should be initialized by the CPU. The DMA
itself will then copy linked descriptors to its descriptor registers as required. In addition to manually initializing the first transfer, software
may also cause the LDMA to load the initial descriptor by writing the descriptor address to the LDMA_CHx_LINK register and then set-
ting the corresponding bit the LDMA_LINKLOAD register.
The contents of the descriptor registers are dynamically updated during the DMA transfer. The contents of descriptors in memory are
not edited by the controller.
Some descriptor field values are only used for linked descriptors. For example, the SRCMODE and DSTMODE bits of the
LDMA_CHx_CTRL registers determine if a linked descriptor is using relative or absolute addressing. Software writes to the address
registers will always use absolute addressing and never set these bits. Therefore, these bits are read only.
8.3.1.1 DMA Transfer Size
A DMA transfer is the smallest unit of data that can be transfered by the LDMA. The LDMA supports byte, half-word and word sized
transfers. The SIZE field in the LDMA_CHx_CTRL register specifies the data width of one DMA transfer.
8.3.1.2 Source/Destination Increments
The SRCINC and DSTINC in the LDMA_CHx_CTRL register determines the increment between DMA transfers. The increment is in
units of DMA transfers and using an increment size of 1 will transfer contiguous bytes, half-words, or words depending on the value of
the SIZE field. Multiple unit increments are useful for transferring or packing/unpacking alligned data. For example using an increment
of 4 with a size of BYTE will transfer word aligned bytes. An increment of 2 units with a size of HALFWORD is suitable for the transfer
of word aligned half-word data. The LDMA can also pack or unpack data by using a different increment size for source and destination.
For example - to convert from word aligned byte data (unpacked) to contiguous byte data (packed), set the SIZE to BYTE, SRCINC to
4, and DSTINC to 1.
SIZE may also be set to NONE which will cause the LDMA to read or write the same location for every DMA transfer. This is usefull for
accessing peripheral FIFO or data registers.
Reference Manual
LDMA - Linked DMA Controller
silabs.com
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