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19.5.2 LEUARTn_CMD - Command Register (Async Reg)
For more information about asynchronous registers see
4.3 Access to Low Energy Peripherals (Asynchronous Registers)
Offset
Bit Position
0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
Access
W1
W1
W1
W1
W1
W1
W1
W1
Name
Bit
Name
Reset
Access Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in
7
CLEARRX
0
W1
Clear RX
Set to clear receive buffer and the RX shift register.
6
CLEARTX
0
W1
Clear TX
Set to clear transmit buffer and the TX shift register.
5
RXBLOCKDIS
0
W1
Receiver Block Disable
Set to clear RXBLOCK, resulting in all incoming frames being loaded into the receive buffer.
4
RXBLOCKEN
0
W1
Receiver Block Enable
Set to set RXBLOCK, resulting in all incoming frames being discarded.
3
TXDIS
0
W1
Transmitter Disable
Set to disable transmission.
2
TXEN
0
W1
Transmitter Enable
Set to enable data transmission.
1
RXDIS
0
W1
Receiver Disable
Set to disable data reception. If a frame is under reception when the receiver is disabled, the incoming frame is discarded.
0
RXEN
0
W1
Receiver Enable
Set to activate data reception on LEUn_RX.
Reference Manual
LEUART - Low Energy Universal Asynchronous Receiver/Transmitter
silabs.com
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