2.2 Block Diagrams
The block diagram for the EFR32 System-On-Chip series is shown in (
Figure 2.1 EFR32 System-On-Chip Block Diagram on page
).
Timers and Triggers
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports
Analog I/F
Lowest power mode with peripheral operational:
USART
Low Energy
UART
TM
I
2
C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
ADC
VDAC
Analog
Comparator
EM3—Stop
EM2—Deep Sleep
EM1—Sleep
EM4—Hibernate
EM4—Shutoff
EM0—Active
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator
Voltage Monitor
Power-On Reset
Other
Op-Amp
IDAC
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
RFSENSE
MOD
FRC
RAC
Frequency
Synthesizer
PGA
PA
I
Q
RF Frontend
LNA
RFSENSE
PA
I
Q
RF Frontend
LNA
To 2.4 GHz receive
I/Q mixers and PA
To Sub GHz
receive I/Q
mixers and PA
To Sub GHz
and 2.4 GHz PA
Sub GHz
2.4 GHz
BALUN
CRYPTO
CRC
True Random
Number Generator
SMU
Core / Memory
ARM Cortex
TM
M4 processor
with DSP extensions, FPU and MPU
Debug Interface
RAM Memory
LDMA Controller
Flash Program
Memory
Real Time
Counter and
Calendar
Cryotimer
Timer/Counter
Low Energy
Timer
Pulse Counter
Watchdog Timer
Protocol Timer
Low Energy
Sensor Interface
Clock Management
H-F Crystal
Oscillator
L-F Crystal
Oscillator
L-F
RC Oscillator
H-F
RC Oscillator
Auxiliary H-F RC
Oscillator
Ultra L-F RC
Oscillator
Figure 2.1. EFR32 System-On-Chip Block Diagram
Reference Manual
System Overview
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