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7.3.7 Flash Startup
On transitions from EM2/3 to EM0, the flash must be powered up. The time this takes depends on the current operating conditions. To
have a deterministic startup-time, set STDLY0 in MSC_STARTUP to 0x64 and clear STDLY1, ASTWAIT, STWSEN and STWS. This will
result in a 10 us delay before the flash is ready. The system will wake up before this, but the Cortex will stall on the first access to the
flash until it is ready. Execute code from RAM or cache to get a quicker startup.
To get the fastest possible startup when waking, i.e. a startup that depends on the current operating conditions, set STDLY0 to 0x28
and set ASTWAIT in MSC_STARTUP. When configured this way, the system will poll the flash to determine when it is ready, and then
start execution.
For even quicker startup, run code in beginning with a set of wait-states. Set STDLY0 to 0x32, STDLY1 to 0x32, and set ASTWAIT and
STWSEN. Then configure STWS in MSC_STARTUP to the number of waitstates to run with. With this setup, sampling will begin with
the given number of waitstates after 5 us, and the system will run with this number of waitstates for the remaining 5 us before returning
to normal operation
A recommended setting for MSC_STARTUP register is to leave STDLY0 at its reset value and set ASTWAIT to one for active sampling
Set STWSEN to zero to bypass the second delay period.
Flash wakeup on demand is supported when wakeup from EM2/3 to EM0. Set bit PWRUPONDEMAND of register MSC_CTRL to one
to enable the power up on demand. When enabled during powerup, flash will enter sleep mode and waiting for either pending flash
read transaction or software command to MSC_CMD.PWRUP bit. If software command wakeup, and interrupt of MSC_IF.PWRUPF will
be flaged if the MSC_IEN.PWRUPF is set
7.3.8 Wait-states
Table 7.5. Flash Wait-States
Wait-States
Frequency
WS0
no more than 25 MHz
WS1
above 25 MHz and no more than 40 MHz
7.3.8.1 One Wait-state Access
After reset, the HFCORECLK is normally 19 MHz from the HFRCO and the MODE field of the MSC_READCTRL register is set to WS1
(one wait-state). The reset value must be WS1 as an uncalibrated HFRCO may produce a frequency higher than 26 MHz. Software
must not select a zero wait-state mode unless the clock is guaranteed to be 26 MHz or below, otherwise the resulting behavior is unde-
fined. If a HFCORECLK frequency above 26 MHz is to be set by software, the MODE field of the MSC_READCTRL register must be
set to WS1 or WS1SCBTP before the core clock is switched to the higher frequency clock source.
When changing to a lower frequency, the MODE field of the MSC_READCTRL register must be set to WS0 or WS0SCBTP only after
the frequency transition has completed. If the HFRCO is used, wait until the oscillator is stable on the new frequency. Otherwise, the
behavior is unpredictable.
To run at a frequency higher than 40 MHz, WS2 or WS2SCBTP must be selected to insert two wait-states for every flash access.
7.3.8.2 Zero Wait-state Access
At 26 MHz and below, read operations from flash may be performed without any wait-states. Zero wait-state access greatly improves
code execution performance at frequencies from 26 MHz and below. By default, the Cortex-M4 uses speculative prefetching and If-
Then block folding to maximize code execution performance at the cost of additional flash accesses and energy consumption.
7.3.8.3 Operation Above
To run at frequencies higher than 26 MHz, MODE in MSC_READCTRL must be set to WS1 or WS1SCBTP.
Reference Manual
MSC - Memory System Controller
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