EURA SD20-G Series, Руководство пользователя

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SD20-G Series
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register in R area, the result sends to no.3 register in R area;
SUBDDP D1 P2 R3 R3=D1-P2
Immediate operand subtracted to the value of P register, the
result sends to no.3 register in R area;
SUBDRP R1 P2 R3 R3=R1-P2
The value of R register subtracted to the value of P register, the
result sends to no.3 register in R area;
SUBDPP P1 P2 P3 R3=P1-P2
The values of two registers in P area are subtracted, the result
sends to no.3 register in R area;
(3) Multiplying Instruction
There are 12 multiplying instructions, which are 16-bit and 32-bit multiplication, see details as below:
a) 16-bit Multiplication:
Instruction Format: [MULW□□ X Y Z]
Instruction Description:
MULW is multiplying instruction, □□ is instruction execution register area; X
is multiplier, Y is multiplicand, Z is store result area; The result of instruction execution is Z=X*Y, which
means that the value of register address in X area multiplied to the value of register address in Y area, the
result sends to Z register address; User can operate for R area, P area and immediate operand; See details
as table 8.1.7.
Table 8.1.7 16-bit Multiplying Instruction Syntax, Results and related Annotations
Syntax Expression Running Results Annotations
MULWRR R1 R2 R3 R4 R3=R1*R2
Multiplying the value of 2 registers in R area, get the
32-bit result, storing to no.3 and no.4 register in R area
respectively, of which no.4 stores high 16-bit, no.3 stores
low 16-bit.
MULWDR D1 R2 R3 R4 R3=1*R2
Multiplying immediate operand and the value of R
register, get 32-bit result, storing to no.3 and no.4 registers
in R area respectively, of which no.4 stores high 16-bit,
no.3 stores low 16-bit.
MULWPR P1 R2 R3 R4 R3=Po001*R2
Multiplying the values of P register and R register, get the
32-bit result, storing to no.3 and no.4 registers in R area
respectively, of which no.4 stores high 16-bit, no.3 stores
low 16-bit.
MULWDP D1 P2 R3 R4 R3=1*Po002
Multiplying immediate operand and the value of P
register, get the 32-bit result, storing to no.3 and no.4
registers in R area, of which no.4 stores high 16-bit, no.3
stores low 16-bit.