EURA SD20-G Series, Руководство пользователя

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SD20-G Series
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XOR B0 ^
（
B0
） B0 register address executes “xor” instruction with last
instruction;
XORI B1 ^
（！
B1
）
Reversing the content of B1 register address, then executes“xor”
instruction with last instruction;
(5) Logical Inversion Instruction
Instruction Format: [INV X]
Instruction Description:
INV is logic instruction;X means register address; Reversing the content of X register address;
Syntax Expression Running Result Annotations
INV B0 !B0 Reversing the content of B0 register address;
(6) Shift Instruction
Shift instruction can be divided into left shift and right shift, can also be divided into signed number and
unsigned number based on data type, see details as tables below:
Table 8.1.15 16-bit Unsigned Left Shift
Syntax Expression Running Result Annotations
SHLWR R1 D1 R1=R1<<1 The content of R1 register shift left one bit
SHLWR P1 D1 Po001=Po001<<1 The content of P1 register shift left one bit
Table 8.1.16 16-bit Unsigned Right Shift
Syntax Expression Running Result Annotations
SHRWR R1 D1 R1=R1>>1 The content of R1 register shift right one bit
SHRWP P1 D1 Po001=Po001>>1 The content of P1 register shift right one bit
Table 8.1.17 32-bit Unsigned Left Shift
Syntax Expression Running Result Annotations
SHLDR R1 D1 R2 R1=R2 R1<<1
The content of R1 register shift left one bit, of
which high-bit stores to R2 register, low-bit
stores to R1 register;
SHLDP P1 D1 Po002 Po001= Po002 Po001<<1
The content of P1 register shift left one bit , of
which high-bit stores to P2 register, low-bit
stores to P1 register;
Table 8.1.18 32-bit Unsigned Right Shift
Syntax Expression Running Result Annotations
SHRDR R1 D1 R2 R1=R2 R1>>1
The content of R1 register shift right one bit, of
which high-bit stores to R2 register, low-bit stores
to R1 register;