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Figure A-8
Cycle time of the analog output module
Settling time
The settling time (t
2
to t
3
), time between creation of the converted value and this reaching a
specific value on the analog output, is load-dependent. It is necessary to differentiate here
between ohmic, capacitive and inductive load.
Response time
The response time (t
1
up to t
3
), the time from the application of the digital output values in the
internal memory up to the reaching of a specific value on the analog output is, in the least
favorable case, the total of the cycle time and settling time. The least favorable case occurs if
the analog channel was converted shortly before the transfer a new output value and the other
channels were re-converted (cycle time) only after the conversion.
The following figure shows the response time of an analog output channel
W
$
W
=
W
(
W
W
W
Figure A-9
Response time of an analog output channel
t
A
Response time
t
C
Cycle time corresponds to the processing time of the module and the conversion time of the
channel
t
I
Settling time
t
1
New digital output value applied
Appendix
A.3 Reaction times
ET 200iSP
Operating Instructions, 11/2017, A5E00247483-07
347
