Remote Control
FPC1000
261
User Manual 1178.4130.02 ─ 02
Bit number
Meaning
2 to 14
Unused
15
This bit is always 0.
13.14.9 STATus:QUEStionable:POWer Register
This register contains information about possible overload states. It can be read using
the commands
STATus:QUEStionable:POWer:CONDition?
and
STATus:QUEStionable:POWer[:EVENt]?
.
Table 13-12: Meaning of bits in STATus:QUEStionable:POWer register
Bit number
Meaning
0 to 1
Unused
2
IF_Overload
This bit is set if the IF path is overloaded. ’IFOVL’ is displayed.
3 to 14
Unused
15
This bit is always 0.
13.14.10 Application of the Status Reporting Systems
In order to be able to effectively use the status reporting system, the information con-
tained there must be transmitted to the controller and further processed there. There
are several methods which are represented in the following.
Service request
Under certain circumstances, the instrument can send a service request (SRQ) to the
controller. Usually this service request initiates an interrupt at the controller, to which
the control program can react appropriately. As evident from Fig. 1-4, an SRQ is
always initiated if one or several of bits 2, 3, 4, 5 or 7 of the status byte are set and
enabled in the SRE. Each of these bits combines the information of a further register,
the error queue or the output buffer. The ENABle parts of the status registers can be
set so that arbitrary bits in an arbitrary status register initiate an SRQ. In order to make
use of the possibilities of the service request effectively, all bits should be set to "1" in
enable registers SRE and ESE.
Example:
Use of the command
*OPC
to generate an SRQ at the end of a sweep.
//Set bit 0 in the ESE (Operation Complete)
CALL InstrWrite(analyzer, "*ESE 1")
//Set bit 5 in the SRE (ESB)
CALL InstrWrite(analyzer, "*SRE 32")
After its settings have been completed, the instrument generates an SRQ.
Status Reporting System
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